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FEATURES
Pretrimmed to 1.0% (AD532K)
No External Components Required
Guaranteed 1.0% max 4-Quadrant Error (AD532K)
Diff Inputs for (X
1
– X
2
) (Y
1
– Y
2
)/10 V Transfer Function
Monolithic Construction, Low Cost
APPLICATIONS
Multiplication, Division, Squaring, Square Rooting
Algebraic Computation
Power Measurements
Instrumentation Applications
Available in Chip Form
+V
S
Internally Trimmed
Integrated Circuit Multiplier
AD532
PIN CONFIGURATIONS
Y
2
Y
1
V
OS
Z
1
OUT
2
14
+V
S
13
Y
1
AD532
TOP VIEW
(Not to Scale)
GND
–V
S 3
NC
4
AD532
12
Y
2
Z
X
2
TOP VIEW
11
V
OS
(Not to Scale)
10
NC
5
GND
NC
6
9
8
X
2
NC
OUT
–V
S
X
1
X
1 7
NC = NO CONNECT
OUT
+V
S
NC
1
3
2
20 19
Y
1
18
Y
2
17
NC
16
V
OS
15
NC
14
GND
–V
S 4
NC
5
NC
6
NC
7
TOP VIEW
(Not to Scale)
PRODUCT DESCRIPTION
NC
8
9
10 11 12 13
The AD532 is the first pretrimmed single chip monolithic multi-
plier/divider. It guarantees a maximum multiplying error of
±
1.0% and a
±
10 V output voltage without the need for any
external trimming resistors or output op amp. Because the
AD532 is internally trimmed, its simplicity of use provides design
engineers with an attractive alternative to modular multipliers,
and its monolithic construction provides significant advantages
in size, reliability and economy. Further, the AD532 can be used
as a direct replacement for other IC multipliers that require
external trim networks.
FLEXIBILITY OF OPERATION
X
1
Z
AD532
NC
NC
NC = NO CONNECT
GUARANTEED PERFORMANCE OVER TEMPERATURE
The AD532 multiplies in four quadrants with a transfer func-
tion of (X
1
– X
2
)(Y
1
– Y
2
)/10 V, divides in two quadrants with
a 10 V Z/(X
1
– X
2
) transfer function, and square roots in one
quadrant with a transfer function of
±√
10 V Z.
In addition to
these basic functions, the differential X and Y inputs provide
significant operating flexibility both for algebraic computation and
transducer instrumentation applications. Transfer functions,
such as XY/10 V, (X
2
– Y
2
)/10 V,
±X
2
/10 V, and 10 V Z/(X
1
– X
2
),
are easily attained and are extremely useful in many modulation
and function generation applications, as well as in trigonometric
calculations for airborne navigation and guidance applications,
where the monolithic construction and small size of the AD532
offer considerable system advantages. In addition, the high
CMRR (75 dB) of the differential inputs makes the AD532
especially well qualified for instrumentation applications, as it
can provide an output signal that is the product of two transducer-
generated input signals.
The AD532J and AD532K are specified for maximum multiplying
errors of
±
2% and
±
1% of full scale, respectively at 25°C, and
are rated for operation from 0°C to 70°C. The AD532S has a
maximum multiplying error of
±
1% of full scale at 25°C; it is
also 100% tested to guarantee a maximum error of
±
4% at the
extended operating temperature limits of –55°C and +125°C. All
devices are available in either the hermetically-sealed TO-100
metal can, TO-116 ceramic DIP or LCC packages. J, K, and
S grade chips are also available.
ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE
MONOLITHIC AD532
1. True ratiometric trim for improved power supply rejection.
2. Reduced power requirements since no networks across sup-
plies are required.
3. More reliable since standard monolithic assembly techniques
can be used rather than more complex hybrid approaches.
4. High impedance X and Y inputs with negligible circuit loading.
5. Differential X and Y inputs for noise rejection and additional
computational flexibility.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
NC
X
2
AD532–SPECIFICATIONS
Model
MULTIPLIER PERFORMANCE
Transfer Function
Total Error (–10 V
≤
X, Y
≤
+10 V)
T
A
= Min to Max
Total Error vs. Temperature
Supply Rejection (± 15 V
±
10%)
Nonlinearity, X (X = 20 V p-p, Y = 10 V)
Nonlinearity, Y (Y = 20 V p-p, X = 10 V)
Feedthrough, X (Y Nulled,
X = 20 V p-p 50 Hz)
Feedthrough, Y (X Nulled,
Y = 20 V p-p 50 Hz)
Feedthrough vs. Temperature
Feedthrough vs. Power Supply
DYNAMICS
Small Signal BW (V
OUT
= 0.1 rms)
1% Amplitude Error
Slew Rate (V
OUT
20 p-p)
Settling Time (to 2%,
∆V
OUT
= 20 V)
NOISE
Wideband Noise f = 5 Hz to 10 kHz
Wideband Noise
f = 5 Hz to 5 MHz
OUTPUT
Output Voltage Swing
Output Impedance (f
≤
1 kHz)
Output Offset Voltage
Output Offset Voltage vs. Temperature
Output Offset Voltage vs. Supply
INPUT AMPLIFIERS (X, Y, and Z)
Signal Voltage Range (Diff. or CM
Operating Diff)
CMRR
Input Bias Current
X, Y Inputs
X, Y Inputs T
MIN
to T
MAX
Z Input
Z Input T
MIN
to T
MAX
Offset Current
Differential Resistance
DIVIDER PERFORMANCE
Transfer Function (X
l
> X
2
)
Total Error
(V
X
= –10 V, –10 V
≤
V
Z
≤
+10 V)
(V
X
= –1 V, –10 V
≤
V
Z
≤
+10 V)
SQUARE PERFORMANCE
Transfer Function
Total Error
SQUARE ROOTER PERFORMANCE
Transfer Function
Total Error (0 V
≤
V
Z
≤
10 V)
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
Operating
Supply Current
Quiescent
PACKAGE OPTIONS
TO-116 (D-14)
TO-100 (H-10A)
LCC (E-20A)
Specifications subject to change without notice.
(@ 25 C, V
S
=
AD532J
Typ
Max
15 V, R
≥
2 k
Min
V
OS
grounded, unless otherwise noted.)
Max
Min
AD532S
Typ
Max
Unit
Min
AD532K
Typ
(X
1
–
X
2
)(Y
1
–
Y
2
)
10
V
(X
1
–
X
2
)(Y
1
–
Y
2
)
10
V
(X
1
–
X
2
)(Y
1
–
Y
2
)
10
V
±
1.5
±
2.5
±
0.04
±
0.05
±
0.8
±
0.3
50
30
2.0
±
0.25
1
75
45
1
0.6
3.0
2.0
±
0.7
±
1.5
±
0.03
±
0.05
±
0.5
±
0.2
30
25
1.0
±
0.25
1
75
45
1
0.6
3.0
1.0
±
0.5
±
0.01
±
0.05
±
0.5
±
0.2
100
80
30
25
1.0
±
0.25
1
75
45
1
0.6
3.0
±
10
30
±
13
1
±
2.5
±
10
50
4
15
1.5
8
±
5
±
25
±
0.1
10
4
1.0
4.0
0.04
%
%
%/°C
%/%
%
%
mV
mV
mV p-p/°C
mV/%
MHz
kHz
V/µs
µs
mV (rms)
mV (rms)
V
Ω
mV
mV/°C
mV/%
200
150
100
80
±
10
±
13
1
±
40
0.7
±
2.5
±
10
±
10
±
13
1
0.7
±
2.5
±
10
30
2.0
40
3
10
±
10
±
30
±
0.3
10
10 V Z/(X
1
– X
2
)
±
2
±
4
(X
1
–
X
2
)
10
V
2
50
1.5
8
±
5
±
25
±
0.1
10
10 V Z/(X
1
– X
2
)
±
1
±
3
(X
1
–
X
2
)
10
V
2
V
dB
µA
µA
µA
µA
µA
MΩ
15
10 V Z/(X
1
– X
2
)
±
1
±
3
(X
1
–
X
2
)
10
V
2
%
%
±
0.8
–√10
V Z
±
1.5
±
15
18
4
6
±
0.4
–√10
V Z
±
1.0
±
15
18
4
6
±
0.4
–√10
V Z
±
1.0
±
15
4
%
%
±
10
±
10
±
10
±
22
6
V
V
mA
AD532JD
AD532JH
AD532KD
AD532KH
AD532SD
AD532SH
AD532SE/883B
THERMAL CHARACTERISTICS
Specifications shown in
boldface
are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those shown
in
boldface
are tested on all production units.
H-10A:
θ
JC
= 25°C/W;
θ
JA
= 150°C/W
E-20A:
θ
JC
= 22°C/W;
θ
JA
= 85°C/W
D-14:
θ
JC
= 22°C/W;
θ
JA
= 85°C/W
–2–
REV. C
AD532
ORDERING GUIDE
CHIP DIMENSIONS AND BONDING DIAGRAM
Model
AD532JD
AD532JD/+
AD532KD
AD532KD/+
AD532JH
AD532KH
AD532JCHIPS
AD532SD
AD532SD/883B
JM38510/13903BCA
AD532SE/883B
AD532SH
AD532SH/883B
JM38510/13903BIA
AD532SCHIPS
Temperature
Ranges
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Package
Descriptions
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Header
Header
Chip
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
LCC
Header
Header
Header
Chip
Package
Options
D-14
D-14
D-14
D-14
H-10A
H-10A
D-14
D-14
D-14
E-20A
H-10A
H-10A
H-10A
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
0.107
(2.718)
V
S
OUTPUT
Z
X
1
0.062
(1.575)
V
S
Y
1
X
2
GND
V
OS
Y
2
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in Figure
1, and the complete schematic in Figure 2. In the multiplying
and squaring modes, Z is connected to the output to close the
feedback around the output op amp. (In the divide mode, it is
used as an input terminal.)
The X and Y inputs are fed to high impedance differential
amplifiers featuring low distortion and good common-mode
rejection. The amplifier voltage offsets are actively laser trimmed
to zero during production. The product of the two inputs is
resolved in the multiplier cell using Gilbert’s linearized trans-
conductance technique. The cell is laser trimmed to obtain
V
OUT
= (X
1
– X
2
)(Y
1
– Y
2
)/10 volts. The built-in op amp is used
to obtain low output impedance and make possible self-contained
operation. The residual output voltage offset can be zeroed at
V
OS
in critical applications . . . otherwise the V
OS
pin should
be grounded.
X
2
R2
Q1
Q2
Q7 Q8
R34
Y
1
X
1
COM
R10
Q5
Q6
Q11
Q12
Q18
R9
R1
Q3
R3
Q4
Q9
R13
Q10
R21
Q14 Q15
Q16 Q17
R20
R22
R6
R8
R16
R23
X
1
V
X
X
2
R
X
Y
1
V
Y
Y
2
(X
1
– X
2
) (Y
1
– Y
2
)
R
10R
R
Z
OUTPUT
V
OS
V
OUT
=
10V
(WITH Z TIED TO OUTPUT)
Figure 1. Functional Block Diagram
V
S
R27
Z
C1
Q21
Q25
V
OS
Q22 Q26
R31
R30
R28
Q23
R29
Q24
R32
R11
R14
R4
R5
Q28
R12
Q13
R15
R24 R25
R26
V
S
CAN
R19
Q19
Q20
Q27
OUTPUT
R33
Y
2
R18
Figure 2. Schematic Diagram
REV. C
–3–
AD532
AD532 PERFORMANCE CHARACTERISTICS
AC FEEDTHROUGH
Multiplication accuracy is defined in terms of total error at
25°C with the rated power supply. The value specified is in
percent of full scale and includes X
IN
and Y
IN
nonlinearities,
feedback and scale factor error. To this must be added such
application-dependent error terms as power supply rejection,
common-mode rejection and temperature coefficients (although
worst case error over temperature is specified for the AD532S).
Total expected error is the rms sum of the individual compo-
nents since they are uncorrelated.
Accuracy in the divide mode is only a little more complex. To
achieve division, the multiplier cell must be connected in the
feedback of the output op amp as shown in Figure 13. In this
configuration, the multiplier cell varies the closed loop gain of the
op amp in an inverse relationship to the denominator voltage.
Thus, as the denominator is reduced, output offset, bandwidth
and other multiplier cell errors are adversely affected. The divide
error and drift are then
m
×
10 V/X
1
– X
2
) where
m
represents
multiplier full-scale error and drift, and (X
1
–X
2
) is the absolute
value of the denominator.
NONLINEARITY
AC feedthrough is a measure of the multiplier’s zero suppression.
With one input at zero, the multiplier output should be zero
regardless of the signal applied to the other input. Feedthrough
as a function of frequency for the AD532 is shown in Figure 5. It
is measured for the condition V
X
= 0, V
Y
= 20 V (p-p) and V
Y
= 0,
V
X
= 20 V (p-p) over the given frequency range. It consists
primarily of the second harmonic and is measured in millivolts
peak-to-peak.
1000
mV
Y FEEDTHROUGH
100
FEEDTHROUGH
10
X FEEDTHROUGH
Nonlinearity is easily measured in percent harmonic distortion.
The curves of Figures 3 and 4 characterize output distortion as
a function of input signal level and frequency respectively, with
one input held at plus or minus 10 V dc. In Figure 4 the sine
wave amplitude is 20 V (p-p).
1.0
1
100
1k
10k
100k
FREQUENCY Hz
1M
10M
Figure 5. Feedthrough vs. Frequency
COMMON-MODE REJECTION
PERCENT DISTORTION
X
IN
0.1
Y
IN
The AD532 features differential X and Y inputs to enhance its
flexibility as a computational multiplier/divider. Common-mode
rejection for both inputs as a function of frequency is shown in
Figure 6. It is measured with X
1
= X
2
= 20 V (p-p), (Y
1
– Y
2
) =
10 V dc and Y
1
= Y
2
= 20 V (p-p), (X
1
– X
2
) = 10 V dc.
70
60
50
Y COMMON-MODE REJ
(X
1
X
2
)
10V
dB
1
2
3
6
7
9
8
4
5
PEAK SIGNAL AMPLITUDE
10 11
Volts
12
13
14
40
30
X COMMON-MODE REJ
10V
(Y
1
Y
2
)
Figure 3. Percent Distortion vs. Input Signal
100
CMRR
0.01
20
10
0
100
1k
10k
100k
FREQUENCY Hz
1M
10M
PERCENT DISTORTION
10
20V p-p SIGNAL
Figure 6. CMRR vs. Frequency
1.0
X
IN
Y
IN
0.1
10
100
1k
10k
FREQUENCY Hz
100k
1M
Figure 4. Percent Distortion vs. Frequency
–4–
REV. C
WindowsCE
