24C32 / 24C64
E
Features
¡
Wide Voltage Operation
- V
CC
= 1.8V to 5.5V
¡
Operating Ambient Temperature: -40
。
to +85
。
C
C
¡
Internally Organized:
- 24C32, 4096 X 8 (32K bits)
- 24C64, 8192 X 8 (64K bits)
¡
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
¡
Write Protect Pin for Hardware Data Protection
¡
32-byte Page (32K, 64K) Write Modes
¡
Partial Page Writes Allowed
¡
Self-timed Write Cycle (5 ms max)
¡
High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
¡
Two-wire Serial Interface
¡
Schmitt Trigger, Filtered Inputs for Noise Suppression
¡
Bidirectional Data Transfer Protocol
¡
8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
¡
Die Sales: Wafer Form, Waffle Pack
General Description
The
24C32/ 24C64 provides 32,768/65,536 bits of serial electrically erasable and programmable read-only memory
24C32/ 24C64 is available in
(EEPROM) organized as 4096/8192 words of 8 bits each. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operation are essential. The
space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface.
Pin Configuration
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A0
A1
A2
GND
8-lead SOP
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A0
A1
A2
GND
8-lead TSSOP
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Pin Descriptions
¡
Table 1: Pin Configuration
Pin Designation
Type
Name and Functions
A0 - A2
SDA
SCL
WP
GND
V
CC
I
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
I/O & Open-drain
I
I
P
P
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24C32 / 24C64
Block Diagram
V
CC
GND
WP
SCL
SDA
START STOP
LOGIC
EN
SERIAL CONTROL
LOGIC
LOAD
COMP
DEVICE ADDRESS
COMPARATOR
HIGH VOLTAGE
PUMP/TIMING
DATA RECOVERY
A0
A1
A2
LOAD
INC
DATA WORD
ADDRESS COUNTER
X DECODER
EEPROM
Y DECODER
SERIAL MUX
DIN
DOUT/ACKNOWLEDGE
DOUT
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24C32 / 24C64
Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0):
The A2, A1 and A0 pins are device address inputs that are hard
wired for the
24C32/ 24C64. Eight 32K/64K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
SERIAL DATA (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
WRITE PROTECT (WP):
The
24C32/ 24C64 has a Write Protect pin that provides hardware data protection. The
Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is
connected to V
CC
, the write protection feature is enabled and operates as shown in the following Table 2.
¡
Table 2: Write Protect
WP Pin Status
Part of the Array Protected
24C32
Full (32K) Array
Normal Read / Write Operations
24C64
Full (64K) Array
At V
CC
At GND
Memory Organization
24C32, 32K SERIAL EEPROM:
Internally organized with 128 pages of 32 bytes each, the 32K requires an 12-bit
data word address for random word addressing.
24C64, 64K SERIAL EEPROM:
Internally organized with 256 pages of 32 bytes each, the 64K requires a 13-bit
data word address for random word address
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24C32 / 24C64
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods
will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see to Figure 2 on page 4).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 2 on page 4).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE:
The
24C32/ 24C64 features a low-power standby mode which is enabled: (a) upon power-up and
(b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any two-wire part can be reset by
following these steps:
1.
2.
3.
Clock up to 9 cycles.
Look for SDA high in each cycle while SCL is high.
Create a start condition.
¡
Figure 1: Data Validity
SDA
SCL
DATA STABLE
DATA
CHANGE
DATA STABLE
¡
Figure 2: Start and Stop Definition
SDA
SCL
START
STOP
BEIJING ESTEK ELECTRONICS CO.,LTD
4
24C32 / 24C64
EE
¡
Figure 3: Output Acknowledge
SCL
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
Device Addressing
The 32K and 64K EEPROM devices all require an 8-bit device address word following a start condition to enable the
chip for a read or write operation (see to Figure 4 on page 7).
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown.
This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 32K/64K EEPROM. These 3 bits must compare to
their corresponding hardwired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a
standby state.
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