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Rev. 1.1, Aug. 2011

K4B1G0446G

K4B1G0846G

1Gb G-die DDR3 SDRAM

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ

-1-

K4B1G0446G

K4B1G0846G

datasheet

History

- First release.

- Corrected Typo.

- Changed timing parameters (Setup/Hold time)

Draft Date

Nov. 2010

Jan. 2011

Jul. 2011

Aug. 2011

Rev. 1.1

DDR3 SDRAM

Revision History

Revision No.

1.0

1.01

1.02

1.03

1.1

Remark

Editor

S.H.Kim

J.Y.Lee

-2-

K4B1G0446G

K4B1G0846G

datasheet

Rev. 1.1

DDR3 SDRAM

Table Of Contents

1Gb G-die DDR3 SDRAM

1. Ordering Information ..................................................................................................................................................... 5

2. Key Features................................................................................................................................................................. 5

3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6

3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6

3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7

3.3 FBGA Package Dimension (x4/x8) .......................................................................................................................... 8

4. Input/Output Functional Description.............................................................................................................................. 9

5. DDR3 SDRAM Addressing ........................................................................................................................................... 10

6. Absolute Maximum Ratings .......................................................................................................................................... 11

6.1 Absolute Maximum DC Ratings............................................................................................................................... 11

6.2 DRAM Component Operating Temperature Range ................................................................................................ 11

7. AC & DC Operating Conditions..................................................................................................................................... 11

7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 11

8. AC & DC Input Measurement Levels ............................................................................................................................ 12

8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12

8.2 V

REF

Tolerances...................................................................................................................................................... 13

8.3 AC & DC Logic Input Levels for Differential Signals............................................................................................... 14

8.3.1. Differential signals definition ............................................................................................................................ 14

8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14

8.3.3. Single-ended requirements for differential signals ........................................................................................... 15

8.4 Differential Input Cross Point Voltage...................................................................................................................... 16

8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 16

8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 16

9. AC & DC Output Measurement Levels ......................................................................................................................... 17

9.1 Single-ended AC & DC Output Levels..................................................................................................................... 17

9.2 Differential AC & DC Output Levels......................................................................................................................... 17

9.3 Single-ended Output Slew Rate .............................................................................................................................. 17

9.4 Differential Output Slew Rate .................................................................................................................................. 18

9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 18

9.6 Overshoot/Undershoot Specification ....................................................................................................................... 19

9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19

9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 19

9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 20

9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 21

9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 21

9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 22

9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 23

9.9 ODT Timing Definitions ........................................................................................................................................... 24

9.9.1. Test Load for ODT Timings.............................................................................................................................. 24

9.9.2. ODT Timing Definitions .................................................................................................................................... 24

10. IDD Current Measure Method ..................................................................................................................................... 27

10.1 IDD Measurement Conditions ............................................................................................................................... 27

11. 1Gb DDR3 SDRAM G-die IDD Specification Table .................................................................................................... 36

12. Input/Output Capacitance ........................................................................................................................................... 37

13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866 ...................................................................... 38

13.1 Clock Specification ................................................................................................................................................ 38

13.1.1. Definition for tCK(avg).................................................................................................................................... 38

13.1.2. Definition for tCK(abs).................................................................................................................................... 38

13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 38

13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 38

13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 38

13.1.6. Definition for tERR(nper)................................................................................................................................ 38

13.2 Refresh Parameters by Device Density................................................................................................................. 39

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 39

13.3.1. Speed Bin Table Notes .................................................................................................................................. 43

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K4B1G0446G

K4B1G0846G

datasheet

Rev. 1.1

DDR3 SDRAM

14. Timing Parameters by Speed Grade .......................................................................................................................... 44

14.1 Jitter Notes ............................................................................................................................................................ 50

14.2 Timing Parameter Notes........................................................................................................................................ 51

14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 52

14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 59

-4-

K4B1G0446G

K4B1G0846G

datasheet

DDR3-1066 (7-7-7)

K4B1G0446G-BCF8

K4B1G0846G-BCF8

DDR3-1333 (9-9-9)

K4B1G0446G-BCH9

K4B1G0846G-BCH9

DDR3-1600 (11-11-11)

K4B1G0446G-BCK0

K4B1G0846G-BCK0

Rev. 1.1

DDR3 SDRAM

1. Ordering Information

[ Table 1 ] Samsung 1Gb DDR3 G-die ordering information table

Organization

256Mx4

128Mx8

DDR3-1866 (13-13-13)

K4B1G0446G-BCMA

K4B1G0846G-BCMA

Package

78 FBGA

NOTE

1. Speed bin is in order of CL-tRCD-tRP.

2. Backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)

3. Backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

4. Backward compatible to DDR3-1066(7-7-7)

2. Key Features

[ Table 2 ] 1Gb DDR3 G-die Speed bins

Speed

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

tRAS(min)

tRC(min)

DDR3-800

6-6-6

2.5

37.5

52.5

DDR3-1066

7-7-7

1.875

13.125

37.5

50.625

DDR3-1333

9-9-9

1.5

13.5

49.5

DDR3-1600

11-11-11

1.25

13.75

48.75

DDR3-1866

13-13-13

1.07

13.91

47.91

Unit

nCK

• JEDEC standard 1.5V ± 0.075V Power Supply

• V

DDQ

= 1.5V ± 0.075V

• 400 MHz f

for 800Mb/sec/pin, 533MHz f

for 1066Mb/sec/pin,

667MHz f

for 1333Mb/sec/pin, 800MHz f

for 1600Mb/sec/pin

900MHz f

for 1866Mb/sec/pin

• 8 Banks

• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13

• Programmable Additive Latency: 0, CL-2 or CL-1 clock

• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6

(DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866)

• 8-bit pre-fetch

• Burst Length: 8 (Interleave without any limit, sequential with starting

address “000” only), 4 with tCCD = 4 which does not allow seamless

read or write [either On the fly using A12 or MRS]

• Bi-directional Differential Data-Strobe

• Internal(self) calibration : Internal self calibration through ZQ pin

(RZQ : 240 ohm ± 1%)

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower than T

CASE

85°C, 3.9us at

85°C < T

CASE

< 95

°C

• Asynchronous Reset

• Package : 78 balls FBGA - x4/x8

• All of Lead-Free products are compliant for RoHS

• All of products are Halogen-free

The 1Gb DDR3 SDRAM G-die is organized as a 32Mbit x 4 I/Os x 8banks,

16Mbit x 8 I/Os x 8banks device. This synchronous device achieves high

speed double-data-rate transfer rates of up to 1866Mb/sec/pin (DDR3-

1866) for general applications.

The chip is designed to comply with the following key DDR3 SDRAM fea-

tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,

On Die Termination using ODT pin and Asynchronous Reset .

All of the control and address inputs are synchronized with a pair of exter-

nally supplied differential clocks. Inputs are latched at the crosspoint of dif-

ferential clocks (CK rising and CK falling). All I/Os are synchronized with a

pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-

ion. The address bus is used to convey row, column, and bank address

information in a RAS/CAS multiplexing style. The DDR3 device operates

with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V

DDQ

The 1Gb DDR3 G-die device is available in 78ball FBGAs(x4/x8).

NOTE

: 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing

Diagram”.

2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.

-5-

参数对比

与K4B1G0846G-BCH9000相近的元器件有：K4B1G0846G-BCH90、K4B1G0846G-BCK00、K4B1G0446G-BCF80、K4B1G0446G-BCMA0、K4B1G0446G-BCH90、K4B1G0446G-BCK00、K4B1G0846G-BCF80、K4B1G0846G-BCMA0。描述及对比如下：

型号	K4B1G0846G-BCH9000	K4B1G0846G-BCH90	K4B1G0846G-BCK00	K4B1G0446G-BCF80	K4B1G0446G-BCMA0	K4B1G0446G-BCH90	K4B1G0446G-BCK00	K4B1G0846G-BCF80	K4B1G0846G-BCMA0
描述	DDR DRAM, 128MX8, 0.255ns, CMOS, PBGA78	DDR DRAM, 128MX8, 0.255ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 128MX8, 0.225ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX4, 0.3ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX4, 0.195ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX4, 0.255ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX4, 0.225ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 128MX8, 0.3ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 128MX8, 0.195ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合	符合
厂商名称	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)
包装说明	FBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compli
最长访问时间	0.255 ns	0.255 ns	0.225 ns	0.3 ns	0.195 ns	0.255 ns	0.225 ns	0.3 ns	0.195 ns
最大时钟频率 (fCLK)	667 MHz	667 MHz	800 MHz	533 MHz	933 MHz	667 MHz	800 MHz	533 MHz	933 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	4,8	4,8	4,8	4,8	4,8	4,8	4,8	4,8	4,8
JESD-30 代码	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78
内存密度	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bi
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	8	8	8	4	4	4	4	8	8
端子数量	78	78	78	78	78	78	78	78	78
字数	134217728 words	134217728 words	134217728 words	268435456 words	268435456 words	268435456 words	268435456 words	134217728 words	134217728 words
字数代码	128000000	128000000	128000000	256000000	256000000	256000000	256000000	128000000	128000000
组织	128MX8	128MX8	128MX8	256MX4	256MX4	256MX4	256MX4	128MX8	128MX8
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	FBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
封装等效代码	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
电源	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	8192	8192	8192	8192	8192
连续突发长度	4,8	4,8	4,8	4,8	4,8	4,8	4,8	4,8	4,8
最大压摆率	0.13 mA	0.13 mA	0.135 mA	0.1 mA	0.135 mA	0.125 mA	0.128 mA	0.105 mA	0.14 mA
标称供电电压 (Vsup)	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
是否无铅	-	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅
零件包装代码	-	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
针数	-	78	78	78	78	78	78	78	78
ECCN代码	-	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	-	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
其他特性	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
长度	-	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm
功能数量	-	1	1	1	1	1	1	1	1
端口数量	-	1	1	1	1	1	1	1	1
工作模式	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	-	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
峰值回流温度（摄氏度）	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
座面最大高度	-	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	-	YES	YES	YES	YES	YES	YES	YES	YES
最大供电电压 (Vsup)	-	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V
最小供电电压 (Vsup)	-	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
温度等级	-	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
处于峰值回流温度下的最长时间	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	-	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm

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