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K4E170811C-BL500

EDO DRAM, 2MX8, 50ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

器件类别:存储    存储   

厂商名称:SAMSUNG(三星)

厂商官网:http://www.samsung.com/Products/Semiconductor/

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器件参数
参数名称
属性值
厂商名称
SAMSUNG(三星)
零件包装代码
SOJ
包装说明
SOJ,
针数
28
Reach Compliance Code
unknown
ECCN代码
EAR99
访问模式
FAST PAGE WITH EDO
最长访问时间
50 ns
其他特性
RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
JESD-30 代码
R-PDSO-J28
长度
18.42 mm
内存密度
16777216 bit
内存集成电路类型
EDO DRAM
内存宽度
8
功能数量
1
端口数量
1
端子数量
28
字数
2097152 words
字数代码
2000000
工作模式
ASYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
2MX8
封装主体材料
PLASTIC/EPOXY
封装代码
SOJ
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
认证状态
Not Qualified
座面最大高度
3.76 mm
自我刷新
YES
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子形式
J BEND
端子节距
1.27 mm
端子位置
DUAL
宽度
7.62 mm
文档预览
K4E170811C, K4E160811C
K4E170812C, K4E160812C
CMOS DRAM
2M x 8Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 2Mx8 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to real-
ize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer and personal
computer.
FEATURES
Part Identification
- K4E170811C-B(F) (5V, 4K Ref.)
- K4E160811C-B(F) (5V, 2K Ref.)
- K4E170812C-B(F) (3.3V, 4K Ref.)
- K4E160812C-B(F) (3.3V, 2K Ref.)
Active Power Dissipation
Unit : mW
Speed
4K
-50
-60
324
288
3.3V
2K
396
360
4K
495
440
5V
2K
605
550
• Extended Data Out Mode operation
(Fast page mode with Extended Data Out)
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
Refresh Cycles
Part
NO.
K4E170811C
K4E170812C
K4E160811C
K4E160812C
V
CC
5V
3.3V
5V
3.3V
2K
32ms
Refresh
cycle
4K
Refresh period
Normal
64ms
128ms
L-ver
RAS
CAS
W
FUNCTIONAL BLOCK DIAGRAM
Control
Clocks
Vcc
Vss
VBB Generator
Data in
Refresh Timer
Refresh Control
Refresh Counter
Memory Array
2,097,152 x8
Cells
Row Decoder
Sense Amps & I/O
Buffer
DQ0
to
DQ7
Performance Range
Speed
-50
-60
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
Remark
5V/3.3V
5V/3.3V
A0-A11
(A0 - A10)
*1
A0 - A8
(A0 - A9)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Data out
Buffer
OE
Note)
*1
: 2K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
K4E170811C, K4E160811C
K4E170812C, K4E160812C
CMOS DRAM
PIN CONFIGURATION
(Top Views)
• K4E17(6)0811(2)C-B
• K4E17(6)0811(2)C-F
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
*A11 is N.C for K4E160811(2)C(5V/3.3V,
2K Ref.
product)
B : 300mil 28 SOJ
F : 300mil 28 TSOP II
Pin Name
A0 - A11
A0 - A10
DQ0 - 7
V
SS
RAS
CAS
W
OE
V
CC
N.C
Pin Function
Address Inputs (4K Product)
Address Inputs (2K Product)
Data In/Out
Ground
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+5V)
Power(+3.3V)
No Connection (2K Ref. product)
K4E170811C, K4E160811C
K4E170812C, K4E160812C
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
3.3V
V
IN,
V
OUT
V
CC
Tstg
P
D
I
OS
Address
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
50
Rating
5V
CMOS DRAM
Units
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
50
V
V
°C
W
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
Min
V
CC
V
SS
V
IH
V
IL
3.0
0
2.0
-0.3
*2
3.3V
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
*1
0.8
Min
4.5
0
2.4
-1.0
*2
5V
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1.0
*1
0.8
V
V
V
V
Units
*1 : V
CC
+1.3V/15ns(3.3V), V
CC
+2.0V/20ns(5V), Pulse width is measured at V
CC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V
SS
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Input Leakage Current (Any input 0≤V
IN
≤V
IN
+0.3V,
all other input pins not under test=0 Volt)
3.3V
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
OH
=-2mA)
Output Low Voltage Level(I
OL
=2mA)
Input Leakage Current (Any input 0≤V
IN
≤V
IN
+0.5V,
all other input pins not under test=0 Volt)
5V
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
OH
=-5mA)
Output Low Voltage Level(I
OL
=4.2mA)
Symbol
I
I(L)
I
O(L)
V
OH
V
OL
I
I(L)
I
O(L)
V
OH
V
OL
Min
-5
-5
2.4
-
-5
-5
2.4
-
Max
5
5
-
0.4
5
5
-
0.4
Units
uA
uA
V
V
uA
uA
V
V
K4E170811C, K4E160811C
K4E170812C, K4E160812C
DC AND OPERATING CHARACTERISTICS
(Continued)
Symbol
Power
Speed
-50
-60
Don′t care
-50
-60
-50
-60
Don′t care
-50
-60
Don′t care
Don′t care
Max
K4E170812C
90
80
1
1
90
80
80
70
0.5
200
90
80
250
200
K4E160812C
110
100
1
1
110
100
90
80
0.5
200
110
100
250
200
K4E170811C
90
80
2
1
90
80
80
70
1
250
90
80
300
250
CMOS DRAM
K4E160811C
110
100
2
1
110
100
90
80
1
250
110
100
300
250
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
mA
mA
mA
uA
uA
I
CC1
Don′t care
Normal
L
Don′t care
I
CC2
I
CC3
I
CC4
Don′t care
Normal
L
Don′t care
L
L
I
CC5
I
CC6
I
CC7
I
CCS
I
CC1
* : Operating Current (RAS and CAS cycling @t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS cycling @t
RC
=min.)
I
CC4
* : Hyper Page Mode Current (RAS=V
IL
, CAS, Address cycling @t
HPC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=0.2V,
DQ=Don′t care, T
RC
=31.25us(4K/L-ver), 62.5us(2K/L-ver),
T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=CAS=V
IL
, W=OE=A0 ~ A11=V
CC
-0.2V or 0.2V,
DQ0 ~ DQ7=V
CC
-0.2V, 0.2V or Open
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Hyper page mode cycle time, t
HPC
.
K4E170811C, K4E160811C
K4E170812C, K4E160812C
CAPACITANCE
(T
A
=25°C, V
CC
=5V or 3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Input capacitance [RAS, CAS, W, OE]
Output capacitance [DQ0 - DQ7]
Symbol
C
IN1
C
IN2
C
DQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
See note 1,2)
Test condition (5V device) : V
CC
=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Test condition (3.3V device) : V
CC
=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
OE to output in Low-Z
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Symbol
Min
-50
Max
Min
104
140
50
13
25
3
3
3
2
30
50
13
38
8
20
15
5
0
10
0
8
25
0
0
0
10
10
13
8
10K
37
25
10K
50
13
3
3
3
2
40
60
15
45
10
20
15
5
0
10
0
10
30
0
0
0
10
10
15
10
10K
45
30
10K
50
15
60
15
30
-60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
4
10
3,4,10
3,4,5
3,10
3
6,14
3
2
Units
Notes
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
CEZ
t
OLZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
84
116
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