K4G323222A
CMOS SGRAM
32Mbit SGRAM
512K x 32bit x 2 Banks
Synchronous Graphic RAM
LVTTL
Revision 1.3
December 2000
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 (Dec. 2000)
-1-
K4G323222A
Revision History
Revision 1.3 (December 12, 2000)
• Removed WPB(Write Per Bit) function.
CMOS SGRAM
Revision 1.2 (August 1, 2000)
• Removed K4G323222A-40
• Changed tSH of K4G323222A from 0.7ns to 1.0ns
Revision 1.1 (June 27, 2000)
• Changed ICC5 of K4G323222A-40/45/50/60/70 :Refer to "DC Characteristics table" on page 6.
Revision 1.0 (June 07, 2000)
• Removed K4G323222A-55 and add K4G323222A-70
Revision 0.3 (March 06, 2000)
•
For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
• Changed tCH/tCL of K4G323222A-60 from 2ns to 2.5ns
Revision 0.0 (January 14, 2000) -
Target Spec
• Define target spec
Rev. 1.3 (Dec. 2000)
-2-
K4G323222A
512K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
•
•
•
•
3.3V power supply
LVTTL compatible with multiplexed address
Dual bank operation
MRS cycle with address key programs
-. CAS Latency (2, 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
32ms refresh period (2K cycle)
100 Pin PQFP, TQFP (14 x 20 mm)
CMOS SGRAM
GENERAL DESCRIPTION
The K4G323222A is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
8 columns block write improves performance in graphics sys-
tems.
•
•
•
•
•
•
ORDERING INFORMATION
Part NO.
K4G323222A-PC/L45
K4G323222A-PC/L50
K4G323222A-PC/L7C
K4G323222A-PC/L60
K4G323222A-PC/L70
K4G323222A-QC/L45
K4G323222A-QC/L50
K4G323222A-QC/L7C
K4G323222A-QC/L60
K4G323222A-QC/L70
Max Freq.
Interface Package
222MHz
200MHz
133MHz@CL2 LVTTL 100 PQFP
166MHz
143MHz
222MHz
200MHz
100 TQFP
133MHz@CL2 LVTTL
166MHz
143MHz
Graphics Features
• SMRS cycle.
-. Load color register
• Block Write(8 Columns)
FUNCTIONAL BLOCK DIAGRAM
DQMi
BLOCK
WRITE
CONTROL
LOGIC
CLK
CKE
CS
WRITE
CONTROL
LOGIC
MASK
COLOR
REGISTER
MUX
INPUT BUFFER
•
COLUMN
MASK
DQMi
DQi
(i=0~31)
TIMING REGISTER
SENSE
AMPLIFIER
RAS
CAS
WE
DSF
DQMi
•
512Kx32
CELL
ARRAY
512Kx32
CELL
ARRAY
ROW DECORDER
BANK SELECTION
•
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW ADDRESS
BUFFER
REFRESH
COUNTER
* Samsung Electronics reserves the right to
change products or specification without
CLOCK ADDRESS(A
0
~A
10
,BA)
notice.
ADDRESS REGISTER
OUTPUT BUFFER
LATENCY &
BURST LENGTH
PROGRAMING
REGISTER
COLUMN
DECORDER
Rev. 1.3 (Dec. 2000)
-3-
K4G323222A
PIN CONFIGURATION
(TOP VIEW)
DQ28
VDDQ
DQ27
DQ26
V
SSQ
DQ25
DQ24
V
DDQ
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
V
SS
V
DD
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C
DQM3
DQM1
CLK
CKE
DSF
N.C
A
8
/AP
CMOS SGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ29
V
SSQ
DQ30
DQ31
V
SS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
DD
DQ0
DQ1
V
SSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 Pin QFP
Forward Type
20 x 14 mm
2
0.65mm pin Pitch
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A
7
A
6
A
5
A
4
V
SS
A
10
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
DD
A
3
A
2
A
1
A
0
*PQFP (Height = 3.0mmMAX)
TQFP (Height = 1.2mmMAX)
PIN CONFIGURATION DESCRIPTION
PIN
CLK
CS
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t
SS
prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
, Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
block write and special mode register set.
Power Supply : +3.3V
±
0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
CKE
Clock Enable
A0 ~ A10
BA
RAS
CAS
WE
DQMi
DQi
DSF
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply /Ground
Data Output Power /Ground
No Connection
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
DQ16
DQ17
V
SSQ
DQ18
DQ19
V
DDQ
V
DD
V
SS
DQ20
DQ21
V
SSQ
DQ22
DQ23
V
DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA
A
9
Rev. 1.3 (Dec. 2000)
-4-
K4G323222A
ABSOLUTE MAXIMUM RATINGS
(Voltage referenced to V
SS
)
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0
~
4.6
-1.0
~
4.6
-55 ~ +150
1
50
CMOS SGRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Output Loading Condition
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
Min
3.0
2.0
-0.3
2.4
-
-10
-10
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
10
see figure 1
Unit
V
V
V
V
V
uA
uA
Note
5
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
Note :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DD.
5. The VDD condition of K4G323222A-45/50/7C/60 is 3.135V~3.6V.
CAPACITANCE
(V
DD
/V
DDQ
= 3.3V, T
A
= 23°C, f = 1MHz)
Pin
Clock
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
-
-
-
-
Max
4.0
4.0
4.0
5.0
Unit
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE, DQM
i
,DSF
Address
DQ
i
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between V
DD
and V
SS
Decoupling Capacitance between V
DDQ
and V
SSQ
Symbol
C
DC1
C
DC2
Value
0.1 + 0.01
0.1 + 0.01
Unit
uF
uF
Note :
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
Rev. 1.3 (Dec. 2000)
-5-
