DDR SDRAM 1Gb M-die (x4, x8)
DDR SDRAM
1Gb M-die SDRAM Specification
66 TSOP-II
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
3. Any system or application incorporating Samsung Memory Product(s) shall be designed to use or access the
memory addresses in a balanced and proportionate manner. Disproportionate, excessive and/or repeated
access to a particular address may result in reduction of product life.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 June. 2005
DDR SDRAM 1Gb M-die (x4, x8)
Table of Contents
DDR SDRAM
1.0 Key Features .............................................................................................................................. 4
2.0 Ordering Information ................................................................................................................ 4
3.0 Operating Frequencies............................................................................................................... 4
4.0 Pin Description .......................................................................................................................... 5
5.0 Package Physical Dimension ................................................................................................... 6
6.0 Block Diagram (64Mbit x4 / 32Mbit x8 I/O x4 Banks) ............................................................... 7
7.0 Input/Output Function Description ........................................................................................... 8
8.0 Command Truth Table ............................................................................................................... 9
9.0 General Description...................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0 DC Operating Conditions ........................................................................................................10
12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11
13.0 Input/Output Capacitance ......................................................................................................11
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12
15.0 DDR SDRAM IDD spec table ..................................................................................................13
16.0 AC Operating Conditions .......................................................................................................14
17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................14
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15
19.0 AC Timming Parameters & Specifications ...........................................................................16
20.0 System Characteristics for DDR SDRAM ............................................................................. 17
21.0 Component Notes ................................................................................................................... 18
22.0 System Notes ..........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 1.1 June. 2005
DDR SDRAM 1Gb M-die (x4, x8)
Revision History
Revision
0.0
0.1
Month
March
March
Year
2003
2003
- First version for internal review
- Complete DDR266 IDD current spec.
- Add A0(DDR200@CL=2.0) speed.
- Drop AA(DDR266@CL=2.0) speed.
- Delete speed A0(CL-tRCD-tRP : 2-2-2) and AA(CL-tRCD-tRP : 2-2-2)
- Correct tRFC to 120ns
- Modified DDR266 IDD current spec.
- Added DDR333 and x16 IDD current spec.
- Modified IDD2N current spec.
- Complete DC current spec.
- Deleted x16 option.
- Finalized datasheet.
- Modified Master Format
History
DDR SDRAM
0.2
0.3
0.4
0.5
0.6
1.0
1.1
June
October
October
November
February
Octber
June
2003
2003
2003
2003
2004
2004
2005
Rev. 1.1 June. 2005
DDR SDRAM 1Gb M-die (x4, x8)
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe
[DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• tRFC(Refresh row cycle time) = 120ns
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
DDR SDRAM
2.0 Ordering Information
Part No.
K4H1G0438M-TC/LB3
K4H1G0438M-TC/LA2
K4H1G0438M-TC/LB0
K4H1G0838M-TC/LB3
K4H1G0838M-TC/LA2
K4H1G0838M-TC/LB0
128M x 8
256M x 4
Org.
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
66pin TSOP II
Interface
Package
3.0 Operating Frequencies
B3(DDR333@CL=2.5)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2.0)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
Rev. 1.1 June. 2005
DDR SDRAM 1Gb M-die (x4, x8)
4.0 Pin Description
DDR SDRAM
128Mb x 8
256Mb x 4
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
A
13
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
A
13
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
Bank Address
BA0~BA1
Auto Precharge
A10
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1Gb TSOP-II Package Pinout
Organization
256Mx4
128Mx8
Row Address
A0~A13
A0~A13
Column Address
A0-A9, A11, A12
A0-A9, A11
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.1 June. 2005
微控制器 MCU
