1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic
DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top
computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other
products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or
notebook computers, cell phones, televisions or visual monitors).
Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung."
3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
February 2004
K4M51163LE - Y(P)C/L/F
FUNCTIONAL BLOCK DIAGRAM
Mobile-SDRAM
I/O Control
LWE
Data Input Register
Bank Select
LDQM
8M x 16
Sense AMP
8M x 16
8M x 16
8M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
LRAS
CLK
CKE
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CS
RAS
CAS
WE
L(U)DQM
February 2004
K4M51163LE - Y(P)C/L/F
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
9
A
B
C
D
1
D
E
F
G
H
J
E
E/2
Pin Name
CLK
D/2
D
e
A
B
C
D
E
F
G
H
J
8
7
6
5
4
3
2
1
1
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
VSS
Mobile-SDRAM
< Top View
*2
>
54Ball(6x9) FBGA
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CAS
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS
BA1
A1
A2
9
VDD
DQ1
DQ3
DQ5
DQ7
WE
CS
A10
VDD
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit:mm]
*2: Top View
CS
CKE
A
0
~ A
12
A
A1
b
BA
0
~ BA
1
RAS
CAS
WE
z
*1: Bottom View
< Top View
*2
>
#A1 Ball Origin Indicator
L(U)DQM
DQ
0
~
15
V
DD
/V
SS
V
DDQ
/V
SSQ
SEC
Week
XXXX
Symbol
A
A
1
E
E
1
D
D
1
e
b
z
Min
1.00
0.27
-
-
-
-
-
0.40
-
Typ
1.10
0.32
11.5
6.40
10.0
6.40
0.80
0.45
-
Max
1.20
0.37
-
-
-
-
-
0.50
0.10
K4M51163LE
February 2004
K4M51163LE - Y(P)C/L/F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
ss
Voltage on V
DD
supply relative to V
ss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
Mobile-SDRAM
Unit
V
V
°C
W
mA
-55 ~ +150
1.0
50
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 70°C)
Parameter
Symbol
V
DD
Supply voltage
V
DDQ
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
V
IH
V
IL
V
OH
V
OL
I
LI
Min
2.3
2.3
1.65
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-10
Typ
2.5
2.5
-
-
0
-
-
-
Max
2.7
2.7
2.7
V
DDQ
+ 0.3
0.3
-
0.2
10
Unit
V
V
V
V
V
V
V
uA
1
2
3
I
OH
= -0.1mA
I
OL
= 0.1mA
4
Note
NOTES :
1. Samsung can support VDDQ 2.5V(in general case) and 1.8V(in specific case) for VDD 2.5V products.
Please contact to the memory marketing team in Samsung Electronics when considering the use of VDDQ 1.8V(Min 1.65V).
2. VIH (max) = 3.0V AC.The overshoot voltage duration is
≤
3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
4. Any input 0V
≤
VIN
≤
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V
≤
VOUT
≤
VDDQ.
CAPACITANCE
(V
DD
= 2.5V,
Pin
Clock
RAS, CAS, WE, CS, CKE
DQM
Address
DQ
0
~ DQ
15
T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Symbol
C
CLK
C
IN
C
IN
C
ADD
C
OUT
Min
3.0
3.0
1.5
3.0
3.0
Max
12.0
12.0
6.0
12.0
6.5
Unit
pF
pF
pF
pF
pF
Note
February 2004
K4M51163LE - Y(P)C/L/F
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 70°C)
Mobile-SDRAM
Version
Parameter
Symbol
Test Condition
-80
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
-1H
-1L
Unit
Note
I
CC1
150
145
130
mA
1
I
CC2
P
1.5
mA
1.5
20
mA
10
8
mA
8
45
mA
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
NS
Input signals are stable
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 10ns
Active Standby Current
in power-down mode
I
CC3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-C
-L
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
40
mA
Operating Current
(Burst Mode)
I
CC
4
230
210
190
mA
1
Refresh Current
I
CC
5
350
320
1800
280
mA
uA
2
4
5
1300
Max 40
850
600
500
Max 70
1300
900
700
uA
°C
Self Refresh Current
I
CC
6
CKE
≤
0.2V
-F
Internal TCSR
Full Array
1/2 of Full Array
1/4 of Full Array
3
6
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported(In commercial Temp : Max 40°C/Max 70°C).
4. K4M51163LE-Y(P)C**
5. K4M51163LE-Y(P)L**
6. K4M51163LE-Y(P)F**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
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