1. In case of 40MHz Frequency, CL1 can be supported.
Address configuration
Organization
16Mx16
Bank
BA0,BA1
Row
A0 - A12
Column Address
A0 - A8
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-
visions may apply.
January 2006
K4M56163LG - R(B)N/G/L/F
FUNCTIONAL BLOCK DIAGRAM
Mobile SDRAM
I/O Control
LWE
Data Input Register
Bank Select
LDQM
4M x 16
Sense AMP
4M x 16
4M x 16
4M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
LRAS
CLK
CKE
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CS
RAS
CAS
WE
L(U)DQM
January 2006
K4M56163LG - R(B)N/G/L/F
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
Mobile SDRAM
< Top View
*2
>
54Ball(6x9) FBGA
9
A
B
C
D
1
D
E
F
G
H
J
D
e
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
1
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
VSS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CAS
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS
BA1
A1
A2
9
VDD
DQ1
DQ3
DQ5
DQ7
WE
CS
A10
VDD
E
Pin Name
CLK
CS
CKE
A
A1
b
A
0
~ A
12
BA
0
~ BA
1
RAS
CAS
WE
L(U)DQM
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit:mm]
z
< Top View
*2
>
DQ
0
~
15
V
DD
/V
SS
V
DDQ
/V
SSQ
#A1 Ball Origin Indicator
SEC Week XXXX
K4M56163LG
Symbol
A
A
1
E
E
1
D
D
1
e
b
z
Min
-
0.25
7.9
-
10.9
-
-
0.45
-
Typ
-
-
8.0
6.40
11.0
6.40
0.80
0.50
-
Max
1.00
-
8.1
-
11.1
-
-
0.55
0.10
January 2006
K4M56163LG - R(B)N/G/L/F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
ss
Voltage on V
DD
supply relative to V
ss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1.0
50
Mobile SDRAM
Unit
V
V
°C
W
mA
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Supply voltage
V
DDQ
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
V
IH
V
IL
V
OH
V
OL
I
LI
2.3
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-10
2.5
-
0
-
-
-
2.7
V
DDQ
+ 0.3
0.3
-
0.2
10
V
V
V
V
V
uA
1
2
3
I
OH
= -0.1mA
I
OL
= 0.1mA
4
Symbol
V
DD
Min
2.3
Typ
2.5
Max
2.7
Unit
V
Note
1
NOTES :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VIH (max) = 3.0V AC.The overshoot voltage duration is
≤
3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
4. Any input 0V
≤
VIN
≤
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V
≤
VOUT
≤
VDDQ.
CAPACITANCE
(V
DD
= 2.5V,
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
DQ
0
~ DQ
15
T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
1.5
1.5
1.5
2.0
Max
3.5
3.0
3.0
4.5
Unit
pF
pF
pF
pF
Note
January 2006
K4M56163LG - R(B)N/G/L/F
DC CHARACTERISTICS
Mobile SDRAM
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Version
Parameter
Symbol
Test Condition
-75
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
-1H
-1L
Unit
Note
I
CC1
80
80
80
mA
1
I
CC2
P
1.0
mA
1.0
15
mA
5
8
mA
8
30
mA
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
Precharge Standby Current
in non power-down mode
I
CC2
NS
Active Standby Current
in power-down mode
I
CC3
P
I
CC3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-N/L
Internal TCSR
45
*5
450
400
350
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
20
mA
Operating Current
(Burst Mode)
I
CC
4
90
80
80
mA
1
Refresh Current
I
CC
5
120
110
600
110
mA
uA
2
85/70
600
450
400
°C
3
Self Refresh Current
I
CC
6
CKE
≤
0.2V
-G/F
Full Array
1/2 of Full Array
1/4 of Full Array
uA
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : 45°C/70°C, In extended Temp : 45°C/85°C
4. It has +/-5
°C
tolerance.
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
在动态调节高功率线性稳压器发明之前，LED 电子产品设计人员配置多个 LED 串主要有两种选项： 采用开关稳压器分别调节每个串;或者使用串并联配置碰运气。 使用开关稳压器调节每个 LED 串(通常在降压配置中)可针对电源波动、LED 堆栈电压波动以及故障保护提供最高级别的灵活性。但是，为每串提供开关稳压器可能成本很高，而且在 LED 串之间正向电压匹配相对较好时也没有必要。另外，以串并联配置安放...[详细]
Altera SoC
