1. In case of 40MHz Frequency, CL1 can be supported.
Address configuration
Organization
8Mx32
Bank
BA0,BA1
Row
A0 - A11
Column Address
A0 - A8
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TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-
visions may apply.
February 2006
K4M56323LG - F(H)N/G/L/F
FUNCTIONAL BLOCK DIAGRAM
Mobile-SDRAM
I/O Control
LWE
Data Input Register
Bank Select
LDQM
2M x 32
Sense AMP
2M x 32
2M x 32
2M x 32
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
LRAS
CLK
CKE
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CS
RAS
CAS
WE
DQM
February 2006
K4M56323LG - F(H)N/G/L/F
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
9
A
B
C
D
D
E
F
G
D
1
H
J
K
L
M
N
P
R
E
Pin Name
CLK
CS
A
A1
b
CKE
A
0
~ A
11
e
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
DQ26
DQ28
V
SSQ
V
SSQ
V
DDQ
V
SS
A4
A7
CLK
DQM1
V
DDQ
V
SSQ
V
SSQ
DQ11
DQ13
2
DQ24
V
DDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
V
DDQ
DQ15
Mobile-SDRAM
< Top View
*2
>
90Ball(6x15) FBGA
3
V
SS
V
SSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
V
SS
DQ9
DQ14
V
SSQ
V
SS
7
V
DD
V
DDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS
V
DD
DQ6
DQ1
V
DDQ
V
DD
8
DQ23
V
SSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
V
SSQ
DQ0
9
DQ21
DQ19
V
DDQ
V
DDQ
V
SSQ
V
DD
A1
A11
RAS
DQM0
V
SSQ
V
DDQ
V
DDQ
DQ4
DQ2
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit:mm]
z
BA
0
~ BA
1
RAS
CAS
WE
DQM
0
~ DQM
3
DQ
0
~
31
< Top View
*2
>
#A1 Ball Origin Indicator
K4M56323LG-XXXX
SAMSUNG
Week
V
DD
/V
SS
V
DDQ
/V
SSQ
Symbol
A
A
1
E
E
1
D
D
1
e
b
z
Min
-
0.25
7.90
-
12.90
-
-
0.45
-
Typ
-
-
8.00
6.40
13.00
11.20
0.80
0.50
-
Max
1.00
-
8.10
-
13.10
-
-
0.55
0.10
February 2006
K4M56323LG - F(H)N/G/L/F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
ss
Voltage on V
DD
supply relative to V
ss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
Mobile-SDRAM
Unit
V
V
°C
W
mA
-55 ~ +150
1.0
50
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Supply voltage
V
DDQ
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
V
IH
V
IL
V
OH
V
OL
I
LI
2.3
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-2
2.5
-
0
-
-
-
2.7
V
DDQ
+ 0.3
0.3
-
0.2
2
V
V
V
V
V
uA
1
2
3
I
OH
= -0.1mA
I
OL
= 0.1mA
4
Symbol
V
DD
Min
2.3
Typ
2.5
Max
2.7
Unit
V
Note
1
NOTES :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VIH (max) = 3.0V AC.The overshoot voltage duration is
≤
3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
4. Any input 0V
≤
VIN
≤
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V
≤
VOUT
≤
VDDQ.
CAPACITANCE
(V
DD
= 2.5V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE
DQM
Address
DQ
0
~ DQ
31
Symbol
C
CLK
C
IN
C
IN
C
ADD
C
OUT
Min
1.5
1.5
1.5
1.5
2.0
Max
3.5
3.0
3.0
3.0
4.5
Unit
pF
pF
pF
pF
pF
Note
February 2006
K4M56323LG - F(H)N/G/L/F
DC CHARACTERISTICS
Mobile-SDRAM
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Version
Parameter
Symbol
Test Condition
-60
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
-75
-7L
Unit
Note
I
CC1
100
90
90
mA
1
I
CC2
P
1.0
mA
1.0
15
mA
5
8
mA
8
25
mA
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
Precharge Standby Current
in non power-down mode
I
CC2
NS
Active Standby Current
in power-down mode
I
CC3
P
I
CC3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-N/L
Internal TCSR
45
*5
450
400
350
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
15
mA
Operating Current
(Burst Mode)
I
CC
4
160
130
130
mA
1
Refresh Current
I
CC
5
180
160
600
160
mA
uA
2
85/70
600
450
400
°C
3
Self Refresh Current
I
CC
6
CKE
≤
0.2V
-G/F
Full Array
1/2 of Full Array
1/4 of Full Array
uA
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : 45°C/70°C, In extended Temp : 45°C/85°C
4. It has +/-5
°C
tolerance.
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
