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K4R571669D/K4R881869D

Direct RDRAM

™

256/288Mbit RDRAM (D-die)

512K x 16/18bit x 32s banks

Direct RDRAM



Version 1.4

July 2002

Page -1

Version 1.4 July 2002

K4R571669D/K4R881869D

Change History

Direct RDRAM

™

Version 1.4( July 2002)

- First Copy ( Version 1.4 is named to unify the version of component and device operation datasheets)

- Based on the 256/288Mb A-die RDRAM



Version 1.4

Page 0

Version 1.4 July 2002

K4R571669D/K4R881869D

Overview

The RDRAM



device is a general purpose high-perfor-

mance memory device suitable for use in a broad range of

applications including computer memory, graphics, video,

and any other application where high bandwidth and low

latency are required.

The 256/288-Mbit RDRAM devices are extremely high-

speed CMOS DRAMs organized as 16M words by 16 or 18

bits. The use of Rambus Signaling Level (RSL) technology

permits up to 1066 MHz transfer rates while using conven-

tional system and board design technologies. RDRAM

devices are capable of sustained data transfers up to 0.938ns

per two bytes (7.5ns per sixteen bytes).

The architecture of RDRAM devices allows the highest

sustained bandwidth for multiple, simultaneous randomly

addressed memory transactions. The separate control and

data buses with independent row and column control yield

over 95% bus efficiency. The RDRAM device's 32 banks

support up to four simultaneous transactions.

System oriented features for mobile, graphics and large

memory systems include power management, byte masking,

and x18 organization. The two data bits in the x18 organiza-

tion are general and can be used for additional storage and

bandwidth or for error correction.

Direct RDRAM

™

SAMSUNG 230

K4RXXXX69D-Fxxx

Figure 1: Direct RDRAM CSP Package

The 256/288-Mbit RDRAM devices are offered in a CSP

horizontal package suitable for desktop as well as low-

profile add-in card and mobile applications.

Key Timing Parameters/Part Numbers

Speed

Organization

Bin

I/O

Freq.

MHz

1066

800

1066

800

RAC

(Row

Access

Time) ns

32P

Features

♦

Highest sustained bandwidth per DRAM device

Part Number

- 2.1GB/s sustained data transfer rate

- Separate control and data buses for maximized

efficiency

- Separate row and column control buses for

easy scheduling and highest performance

- 32 banks: four transactions can take place simul-

taneously at full bandwidth data rates

♦

Low latency features

-CT9

-CN9

512Kx16x32s

-CM9

-CM8

-CK8

-CT9

-CN9

512Kx18x32s

-CM9

-CM8

-CK8

K4R571669D-F

K4R571669D-FCN9

K4R571669D-FCM9

K4R571669D-FCM8

K4R571669D-FCK8

K4R881869D-FCT9

K4R881869D-FCN9

K4R881869D-FCM9

K4R881869D-FCM8

K4R881869D-FCK8

- Write buffer to reduce read latency

- 3 precharge mechanisms for controller flexibility

- Interleaved transactions

♦

Advanced power management:

- Multiple low power states allows flexibility in power

consumption versus time to transition to active state

- Power-down self-refresh

♦

Organization: 2kbyte pages and 32 banks, x 16/18

a.“32s” - 32 banks which use a

“split”

bank architecture.

b.“F” - WBGA package.

c.“C” - RDRAM core uses normal power self refresh.

- x18 organization allows ECC configurations or

increased storage/bandwidth

- x16 organization for low cost applications

♦

Uses Rambus Signaling Level (RSL) for up to 1066MHz

operation

Page 1

Version 1.4 July 2002

K4R571669D/K4R881869D

Pinouts and Definitions

Center-Bonded Devices

These tables shows the pin assignments of the center-bonded

RDRAM package. The mechanical dimensions of this

Direct RDRAM

™

package are shown in a later section. Refer to Section

“Center-Bonded

WBGA Package” on page 18. Note - pin #1

is at the A1 position.

Table 1: Center-Bonded Device (top view)

ROW

COL

GND

DQA6

DQA4

DQA2

DQA0

CFM

CFMN

RQ6

RQ4

RQ2

RQ0

DQB0

DQB2

DQB4

DQB6

GND

DQA8

CMD

DQA5

GND

GNDa

CTM

RQ7

GND

RQ1

DQB1

GND

CMOS

DQB7

DQB8

GND

DQA7

DQA3

DQA1

CTMN

RQ5

RQ3

DQB3

DQB5

GND

SCK

CMOS

GND

DDa

REF

GND

SIO0

SIO1

GND

SAMSUNG 230

K4RXXXX69D-Fxxx

Top View

Chip

The pin #1(ROW 1, COL A) is located at the

A1 position on the top side and the A1 position

is marked by the marker

“ ”

Page 2

Version 1.4 July 2002

K4R571669D/K4R881869D

Direct RDRAM

™

Table 2: Pin Description

Signal

SIO1,SIO0

CMD

I/O

Type

CMOS

# Pins

center

Description

Serial input/output. Pins for reading from and writing to the control regis-

ters using a serial access protocol. Also used for power management.

Command input. Pins used in conjunction with SIO0 and SIO1 for reading

from and writing to the control registers. Also used for power manage-

ment.

Serial clock input. Clock source used for reading from and writing to the

control registers

Supply voltage for the RDRAM core and interface logic.

Supply voltage for the RDRAM analog circuitry.

Supply voltage for CMOS input/output pins.

Ground reference for RDRAM core and interface.

Ground reference for RDRAM analog circuitry.

Data byte A. Nine pins which carry a byte of read or write data between

the Channel and the RDRAM device. DQA8 is not used (no connection)

by RDRAM device with a x16 organization.

Clock from master. Interface clock used for receiving RSL signals from

the Channel. Positive polarity.

Clock from master. Interface clock used for receiving RSL signals from

the Channel. Negative polarity

Logic threshold reference voltage for RSL signals

Clock to master. Interface clock used for transmitting RSL signals to the

Channel. Negative polarity.

Clock to master. Interface clock used for transmitting RSL signals to the

Channel. Positive polarity.

Row access control. Three pins containing control and address informa-

tion for row accesses.

Column access control. Five pins containing control and address informa-

tion for column accesses.

Data byte B. Nine pins which carry a byte of read or write data between

the Channel and the RDRAM device. DQB8 is not used (no connection)

by RDRAM device with a x16 organization.

SCK

DDa

CMOS

GND

GNDa

DQA8..DQA0

CMOS

I/O

RSL

CFM

CFMN

REF

CTMN

CTM

RQ7..RQ5 or

ROW2..ROW0

RQ4..RQ0 or

COL4..COL0

DQB8..

DQB0

RSL

I/O

RSL

Total pin count per package

a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.

b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.

Page 3

Version 1.4 July 2002

参数对比

与K4R571669D-FCM80相近的元器件有：K4R571669D-FCN90、K4R571669D-FCT90、K4R881869D-FCT90、K4R571669D-FCM90、K4R881869D-FCM80、K4R881869D-FCK80、K4R881869D-FCM90、K4R881869D-FCN90、K4R571669D-FCK80。描述及对比如下：

型号	K4R571669D-FCM80	K4R571669D-FCN90	K4R571669D-FCT90	K4R881869D-FCT90	K4R571669D-FCM90	K4R881869D-FCM80	K4R881869D-FCK80	K4R881869D-FCM90	K4R881869D-FCN90	K4R571669D-FCK80
描述	Rambus DRAM, 16MX16, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX16, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX16, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX18, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX16, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX18, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX18, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX18, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX18, CMOS, PBGA92, WBGA-92	Rambus DRAM, 16MX16, CMOS, PBGA92, WBGA-92
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,
针数	92	92	92	92	92	92	92	92	92	92
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL
其他特性	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH
JESD-30 代码	R-PBGA-B92	R-PBGA-B92	R-PBGA-B92	R-PBGA-B92	R-PBGA-B92	R-PBGA-B92	R-PBGA-B92	R-PBGA-B92	R-PBGA-B92	R-PBGA-B92
长度	15.1 mm	15.1 mm	15.1 mm	15.1 mm	15.1 mm	15.1 mm	15.1 mm	15.1 mm	15.1 mm	15.1 mm
内存密度	268435456 bit	268435456 bit	268435456 bit	301989888 bit	268435456 bit	301989888 bit	301989888 bit	301989888 bit	301989888 bit	268435456 bit
内存集成电路类型	RAMBUS DRAM	RAMBUS DRAM	RAMBUS DRAM	RAMBUS DRAM	RAMBUS DRAM	RAMBUS DRAM	RAMBUS DRAM	RAMBUS DRAM	RAMBUS DRAM	RAMBUS DRAM
内存宽度	16	16	16	18	16	18	18	18	18	16
功能数量	1	1	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1	1	1
端子数量	92	92	92	92	92	92	92	92	92	92
字数	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words
字数代码	16000000	16000000	16000000	16000000	16000000	16000000	16000000	16000000	16000000	16000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
组织	16MX16	16MX16	16MX16	16MX18	16MX16	16MX18	16MX18	16MX18	16MX18	16MX16
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.08 mm	1.08 mm	1.08 mm	1.08 mm	1.08 mm	1.08 mm	1.08 mm	1.08 mm	1.08 mm	1.08 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
最大供电电压 (Vsup)	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V
最小供电电压 (Vsup)	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	9.3 mm	9.3 mm	9.3 mm	9.3 mm	9.3 mm	9.3 mm	9.3 mm	9.3 mm	9.3 mm	9.3 mm
厂商名称	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	-	-	-	-	SAMSUNG(三星)
Base Number Matches	1	1	1	1	1	1	1	1	1	-