1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic
DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top
computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other
products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or
notebook computers, cell phones, televisions or visual monitors)
Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung." .
3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur
pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
1
September 2004
K4S51323LF - M(E)C/L/F
FUNCTIONAL BLOCK DIAGRAM
Mobile SDRAM
I/O Control
LWE
Data Input Register
Bank Select
LDQM
4M x 32
Sense AMP
4M x 32
4M x 32
4M x 32
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
LRAS
CLK
CKE
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CS
RAS
CAS
WE
DQM
2
September 2004
K4S51323LF - M(E)C/L/F
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
9
A
B
C
D
D
E
F
G
D
1
H
J
K
D/2
L
M
N
P
R
E
E/2
Pin Name
CLK
CS
A
A1
Substrate(2Layer)
Mobile SDRAM
< Top View
*2
>
90Ball(6x15) FBGA
8
7
6
5
4
3
2
1
e
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
DQ26
DQ28
V
SSQ
V
SSQ
V
DDQ
V
SS
A4
A7
CLK
DQM1
V
DDQ
V
SSQ
V
SSQ
DQ11
DQ13
2
DQ24
V
DDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
V
DDQ
DQ15
3
V
SS
V
SSQ
DQ25
DQ30
NC
A3
A6
A12
A9
NC
V
SS
DQ9
DQ14
V
SSQ
V
SS
7
V
DD
V
DDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS
V
DD
DQ6
DQ1
V
DDQ
V
DD
8
DQ23
V
SSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
V
SSQ
DQ0
9
DQ21
DQ19
V
DDQ
V
DDQ
V
SSQ
V
DD
A1
A11
RAS
DQM0
V
SSQ
V
DDQ
V
DDQ
DQ4
DQ2
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit:mm]
CKE
A
0
~ A
12
BA
0
~ BA
1
RAS
CAS
WE
DQM
0
~ DQM
3
DQ
0
~
31
b
z
< Top View
*2
>
#A1 Ball Origin Indicator
SAMSUNG
Week
3
V
DD
/V
SS
V
DDQ
/V
SSQ
K4S51323LF-XXXX
Symbol
A
A
1
E
E
1
D
D
1
e
b
z
Min
-
0.27
-
-
-
-
-
0.45
-
Typ
1..30
0.32
11.0
6.40
13.0
11.2
0.80
0.50
-
Max
1.40
0.37
-
-
-
-
-
0.55
0.10
September 2004
K4S51323LF - M(E)C/L/F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
ss
Voltage on V
DD
supply relative to V
ss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1.0
50
Mobile SDRAM
Unit
V
V
°C
W
mA
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 70°C)
Parameter
Symbol
V
DD
Supply voltage
V
DDQ
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
NOTES :
2. VIH (max) = 3.0V AC.The overshoot voltage duration is
≤
3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
4. Any input 0V
≤
VIN
≤
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V
≤
VOUT
≤
VDDQ.
Min
2.3
2.3
1.65
Typ
2.5
2.5
-
-
0
-
-
-
Max
2.7
2.7
2.7
V
DDQ
+ 0.3
0.3
-
0.2
2
Unit
V
V
V
V
V
V
V
uA
Note
1
2
3
I
OH
= -0.1mA
I
OL
= 0.1mA
4
V
IH
V
IL
V
OH
V
OL
I
LI
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-2
1. Samsung can support VDDQ 2.5V(in general case) and 1.8V(in specific case) for VDD 2.5V products. Please contact to the
memory marketing team in Samsung Electronics when considering the use of VDDQ 1.8V(Min 1.65V).
CAPACITANCE
(V
DD
= 2.5V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE
DQM
Address
DQ
0
~ DQ
31
Symbol
C
CLK
C
IN
C
IN
C
ADD
C
OUT
Min
3.0
3.0
1.5
3.0
3.0
Max
6.0
6.0
3.0
6.0
5.0
Unit
pF
pF
pF
pF
pF
Note
4
September 2004
K4S51323LF - M(E)C/L/F
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 70°C)
Mobile SDRAM
Version
Parameter
Symbol
Test Condition
-75
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
-1H
-1L
Unit
Note
I
CC1
120
120
110
mA
1
I
CC2
P
1.0
mA
1.0
20
mA
10
8
mA
4
45
mA
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
NS
Input signals are stable
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 10ns
Active Standby Current
in power-down mode
I
CC3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-C
-L
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
30
mA
Operating Current
(Burst Mode)
I
CC
4
170
150
150
mA
1
Refresh Current
I
CC
5
300
280
1500
240
mA
uA
2
4
5
1200
Max 40
900
800
700
Max 70
1200
900
800
uA
°C
Self Refresh Current
I
CC
6
CKE
≤
0.2V
-F
Internal TCSR
Full Array
1/2 of Full Array
1/4 of Full Array
3
6
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported(In commercial Temp : Max 40°C/Max 70°C).
4. K4S51323LF-M(E)C**
5. K4S51323LF-M(E)L**
6. K4S51323LF-M(E)F**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
