SDRAM 256Mb H-die (x4, x8, x16)
CMOS SDRAM
256Mb H-die SDRAM Specification
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* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 October 2005
SDRAM 256Mb H-die (x4, x8, x16)
Revision History
Revision 0.0 (May. 2005)
- First release.
Revision 1.0 (October. 2005)
- Final release.
CMOS SDRAM
Rev. 1.0 October 2005
SDRAM 256Mb H-die (x4, x8, x16)
CMOS SDRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• Pb/Pb-free Package
• RoHS compliant for Pb-free Package
GENERAL DESCRIPTION
The K4S560432H / K4S560832H / K4S561632H is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S560432H-T(U)C/L75
K4S560832H-T(U)C/L75
K4S561632H-T(U)C/L60
K4S561632H-T(U)C/L75
Orgainization
64M x 4
32M x 8
16M x 16
Max Freq.
133MHz (CL=3)
133MHz (CL=3)
166MHz (CL=3)
133MHz (CL=3)
LVTTL
54pin TSOP(II)
Pb (Pb-free)
Interface
Package
Organization
64Mx4
32Mx8
16Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
A0-A8
Row & Column address configuration
Rev. 1.0 October 2005
SDRAM 256Mb H-die (x4, x8, x16)
Package Physical Dimension
CMOS SDRAM
0~8°C
0.25
TYP
0.010
#54
#28
0.45~0.75
0.018~0.030
0.05
MIN
0.002
( 0.50 )
0.020
11.76±
0.20
0.463±
0.008
#1
22.62
MAX
0.891
22.22
0.875
0.10
MAX
0.004
(
0.71
)
0.028
±
0.10
±
0.004
#27
0.21
0.008
±
0.05
±
0.002
1.00
0.039
±
0.10
±
0.004
0.30
-0.05
0.012
+0.004
-0.002
+0.10
0.80
0.0315
54Pin TSOP(II) Package Dimension
Rev. 1.0 October 2005
10.16
0.400
0.125
+0.075
-0.035
0.005
+0.003
-0.001
1.20
MAX
0.047
SDRAM 256Mb H-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
16M x 4 / 8M x 8 / 4M x 16
Sense AMP
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
Programming Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 October 2005
