K4S56163LC-R(B)L/N/P
CMOS SDRAM
16Mx16
SDRAM 54CSP
(VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V)
Revision 1.4
December. 2002
Rev. 1.4 Dec. 2002
K4S56163LC-R(B)L/N/P
4M x 16Bit x 4 Banks Mobile SDRAM in 54CSP
FEATURES
• 2.5V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation(-25°C~70°C).
Extended Temperature Operation(-25°C~85
°C).
Industrial Temperature Operation (-40°C ~ 85°C).
• 54balls CSP (-RXXX - Pb, -BXXX - Pb Free)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S56163LC is 268,435,456 bits synchronous high data rate
Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock and I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst length
and programmable latencies allow the same device to be useful for
a variety of high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
Part No.
K4S56163LC-R(B)L/N/P75
K4S56163LC-R(B)L/N/P1H
K4S56163LC-R(B)L/N/P1L
Max Freq.
133MHz(CL=3)
105MHz(CL=2)
105MHz(CL=2)
105MHz(CL=3)
*1
LVCMOS
54 CSP
Pb
(Pb Free)
Interface Package
K4S56163LC-R(B)L/N/P15 66MHz(CL=2/3)
*2
-R(B)L ; Low Power, Operating Temperature ; -25° C~70°C.
-R(B)N ; Low Power, Operating Temperature ; -25° C~85°C.
-R(B)P : Low Power, Operating Temperature ; -40
°C
~ 85°C.
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
2. In case of 33MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
4M x 16
4M x 16
4M x 16
4M x 16
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 Dec. 2002
K4S56163LC-R(B)L/N/P
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
CMOS SDRAM
< Top View
*2
>
54Ball(6x9) CSP
1
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SS
CKE
A9
A6
A4
7
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
D D
CAS
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS
BA1
A1
A2
9
V
D D
DQ1
DQ3
DQ5
DQ7
WE
CS
A10
V
D D
9
A
B
C
D
1
D
E
F
G
H
J
8
7
6
5
4
3
2
1
e
A
B
C
D
E
F
G
H
J
D/2
D
V
SS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
V
SS
E
E/2
Pin Name
CLK
CS
CKE
A
0
~ A
12
BA
0
~ BA
1
RAS
A
A1
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
*2: Top View
CAS
WE
L(U)DQM
D Q
0
~
15
V
DD
/V
SS
V
DDQ
/V
SSQ
Max. 0.20
Encapsulant
b
z
*1: Bottom View
< Top
View
*2
>
#A1 Ball Origin Indicator
K4S56163LC-XXXX
SAMSUNG
Week
[Unit:mm]
Symbol
A
A
1
E
E
1
D
D
1
e
b
z
Min
0.90
0.30
-
-
-
-
-
0.40
-
Typ
0.95
0.35
8.10
6.40
15.10
6.40
0.80
0.45
-
Max
1.00
0.40
-
-
-
-
-
0.50
0.10
Rev. 1.4 Dec. 2002
K4S56163LC-R(B)L/N/P
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
D D
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T =Commercial, Extended, Industrial Temperature)
A
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
D D
V
DDQ
V
I H
V
IL
V
O H
V
OL
I
LI
Min
2.3
1.65
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-10
Typ
2.5
-
-
0
-
-
-
Max
2.7
2.7
V
DDQ
+ 0.3
0.3
-
0.2
10
Unit
V
V
V
V
V
V
uA
1
2
I
O H
= -0.1mA
I
OL
= 0.1mA
3
Note
Notes :
1. V
IH
(max) = 3.0V AC.The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
Clock
(V
DD
= 2.5V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.0
2.0
2.0
3.5
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Note
RAS, CAS, WE, CS, CKE, DQM
Address
D Q
0
~ DQ
15
Rev. 1.4 Dec. 2002
K4S56163LC-R(B)L/N/P
DC CHARACTERISTICS
CMOS SDRAM
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
=Commercial, Extended, Industrial Temperature)
Parameter
Symbol
Test Condition
-75
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
I
C C 1
Burst length = 1
t
RC
≥
t
R C
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
75
Version
-1H
70
-1L
65
-15
60
mA
1, 3
Unit
Note
I
C C 2
P
I
CC2
PS
I
CC2
N
0.5
0.5
15
mA
Precharge Standby Current
in non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
C C 2
NS
Input signals are stable
I
C C 3
P
I
CC3
PS
I
CC3
N
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-R(B)L
mA
10
6
6
25
mA
Active Standby Current
in power-down mode
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
C C 3
NS
25
mA
Operating Current
(Burst Mode)
Refresh Current
I
C C 4
115
95
95
85
mA
1
I
C C 5
165
155
150
125
mA
2
3
Self Refresh Current
I
C C 6
CKE
≤
0.2V
-R(B)N
-R(B)P
750
uA
4
5
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S56163LC-R(B)L**
4. K4S56163LC-R(B)N**
5. K4S56163LC-R(B)P**
6. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Rev. 1.4 Dec. 2002
