256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
Release to Final Data Sheet.
1.1. Delete Preliminary.
Add 10ns & Low Power Ver.
Preliminary
CCPCCCRCELIMINARY
Draft Data
Aug. 5. 1998
Mar. 3. 1999
Remark
Preliminary
Final
Rev. 2.0
Apr. 24. 2000
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 2.0
April 2000
PRELIMINARY
PRELIMINARY
K6R1004C1C-C/C-L, K6R1004C1C-I/C-P
256K x 4 Bit (with OE) High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-Ver. only
Operating K6R1004C1C-10 : 75mA(Max.)
K6R1004C1C-12 : 70mA(Max.)
K6R1004C1C-15 : 68mA(Max.)
K6R1004C1C-20 : 65mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration :
CMOS SRAM
GENERAL DESCRIPTION
Preliminary
CCPCCCRCELIMINARY
The K6R1004C1C is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 262,144 words by 4 bits.
The K6R1004C1C uses 4 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG′s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
K6R1004C1C is packaged in a 400 mil 32-pin plastic SOJ.
ORDERING INFORMATION
K6R1004C1C-C10/C12/C15/C20
K6R1004C1C-I10/I12/I15/I20
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION
(Top View)
N.C
A
0
1
2
3
4
5
6
7
8
9
32 A
17
31 A
16
30 A
15
29 A
14
28 A
13
27
OE
FUNCTIONAL BLOCK DIAGRAM
A
1
A
2
A
3
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Pre-Charge Circuit
CS
I/O
1
Vcc
26 I/O
4
SOJ
25 Vss
24 Vcc
23 I/O
3
22 A
12
21 A
11
20 A
10
19
18
A
9
A
8
Row Select
Vss
Memory Array
512 Rows
512x4 Columns
I/O
2
10
WE
A
4
A
5
A
6
A
7
11
12
13
14
15
I/O
1
~ I/O
4
Data
Cont.
CLK
Gen.
I/O Circuit &
Column Select
N.C 16
17 N.C
PIN FUNCTION
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Pin Name
A
0
- A
17
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
CS
WE
OE
WE
CS
OE
I/O
1
~ I/O
4
V
CC
V
SS
N.C
-2-
Revision 2.0
April 2000
PRELIMINARY
PRELIMINARY
K6R1004C1C-C/C-L, K6R1004C1C-I/C-P
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
Rating
-0.5 to Vcc+0.5V
Unit
V
V
W
°C
°C
°C
CMOS SRAM
V
CC
-0.5 to 7.0
Preliminary
CCPCCCRCELIMINARY
P
d
1
T
STG
T
A
T
A
-65 to 150
0 to 70
-40 to 85
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5*
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+0.5**
0.8
Unit
V
V
V
V
* V
IL
(Min) = -2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
02ns
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
I
OH1
=-0.1mA
Normal
L-Ver.
Min
-2
-2
-
-
-
-
-
-
-
-
2.4
-
Max
2
2
75
70
68
65
30
5
0.5
0.4
-
3.95
V
V
V
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
V
OH1
*
* V
CC
=5.0V±5%, Temp.=25°C
.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
-3-
Revision 2.0
April 2000
PRELIMINARY
PRELIMINARY
K6R1004C1C-C/C-L, K6R1004C1C-I/C-P
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
Value
0V to 3V
Preliminary
CCPCCCRCELIMINARY
3ns
1.5V
See below
CMOS SRAM
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+5.0V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
480Ω
255
Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address
Chip Selection to Power Up Time
Chip Selection to Power Down-
Sym-
bol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
K6R1004C1C-10
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
K6R1004C1C-12
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
K6R1004C1C-15
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
K6R1004C1C-20
Min
20
-
-
-
3
0
0
0
3
0
-
Max
-
20
20
9
-
-
9
9
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
-4-
Revision 2.0
April 2000
PRELIMINARY
PRELIMINARY
K6R1004C1C-C/C-L, K6R1004C1C-I/C-P
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Sym-
bol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
K6R1004C1C-10
Min
10
7
0
7
7
10
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
K6R1004C1C-12
Min
12
Max
K6R1004C1C-15
Min
Max
K6R1004C1C-20
Min
Max
-
-
-
-
-
-
-
9
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMOS SRAM
-
15
-
20
Preliminary
CCPCCCRCELIMINARY
8
-
9
-
10
0
8
8
-
-
-
-
-
6
-
-
-
0
9
9
15
0
0
7
0
3
-
-
-
-
-
7
-
-
-
0
10
10
20
0
0
8
0
3
12
0
0
6
0
3
* The above parameters are also guaranteed at industrial temperature range.
