K6T4008C1C Family
Document Title
512Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
1.0
History
Initial draft
Finalize
Draft Date
October 20,1998
April 12, 1999
Remark
Preliminary
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
April 1999
K6T4008C1C Family
512Kx8 bit Low Power CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 512Kx8
•
Power Supply Voltage: 4.5~5.5V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 32-DIP-600, 32-SOP-525,
32-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T4008C1C families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and various package
types for user flexibility of system design. The family also
support low data retention voltage for battery back-up oper-
ation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range
Speed
Standby
(I
SB1
, Max)
80µA
4.5~5.5V
Inderstrial (-40~85°C)
55
1)
/70ns
20µA
100µA
30µA
55mA
32-SOP-525
32-TSOP2-400F/R
Operating
(I
CC2
, Max)
PKG Type
K6T4008C1C-L
K6T4008C1C-B
K6T4008C1C-P
K6T4008C1C-F
Commercial (0~70°C)
32-DIP-600, 32-SOP-525
32-TSOP2-400F/R
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
FUNCTIONAL BLOCK DIAGRAM
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O
1
I/O
8
Clk gen.
Precharge circuit.
32-DIP
32-SOP
32-TSOP2
(Forward)
26
25
24
23
22
21
20
19
18
17
32-TSOP2
(Reverse)
7
8
9
10
11
12
13
14
15
16
Row
select
Memory array
1024 rows
512×8 columns
Data
cont
I/O Circuit
Column select
Data
cont
Pin Name
WE
CS
OE
A
0
~A
18
I/O
1
~I/O
8
Vcc
Vss
Function
Write Enable Input
Chip Select Input
Output Enable Input
Address Inputs
Data Inputs/Outputs
Power
Ground
CS
WE
OE
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.0
April 1999
K6T4008C1C Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
K6T4008C1C-DL55
K6T4008C1C-DB55
K6T4008C1C-DL70
K6T4008C1C-DB70
K6T4008C1C-GL55
K6T4008C1C-GB55
K6T4008C1C-GL70
K6T4008C1C-GB70
K6T4008C1C-VB55
K6T4008C1C-VB70
K6T4008C1C-MB55
K6T4008C1C-MB70
Function
32-DIP, 55ns, Low Power
32-DIP, 55ns, Low Low Power
32-DIP, 70ns, Low Power
32-DIP, 70ns, Low Low Power
32-SOP, 55ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Power
32-SOP, 70ns, Low Low Power
32-TSOP2-F, 55ns, Low Low Power
32-TSOP2-F, 70ns, Low Low Power
32-TSOP2-R, 55ns, Low Low Power
32-TSOP2-R, 70ns, Low Low Power
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
K6T4008C1C-GP55
K6T4008C1C-GF55
K6T4008C1C-GP70
K6T4008C1C-GF70
K6T4008C1C-VF55
K6T4008C1C-VF70
K6T4008C1C-MF55
K6T4008C1C-MF70
Function
32-SOP, 55ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Power
32-SOP, 70ns, Low Low Power
32-TSOP2-F, 55ns, Low Low Power
32-TSOP2-F, 70ns, Low Low Power
32-TSOP2-R, 55ns, Low Low Power
32-TSOP2-R, 70ns, Low Low Power
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
OE
X
1)
H
L
X
1)
WE
X
1)
H
H
L
I/O Pin
High-Z
High-Z
Dout
Din
Mode
Deselected
Output disbaled
Read
Write
Power
Standby
Active
Active
Active
1. X means don′t care.( Must be in low or high state.)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
Remark
-
-
-
-
K6T4008C1C-L/-B
K6T4008C1C-P/-F
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
April 1999
K6T4008C1C Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
4.5
0
2.2
-0.5
3)
Typ
5.0
0
-
-
CMOS SRAM
Max
5.5
0
Vcc+0.5
2)
0.8
Unit
V
V
V
V
Note:
1. Commercial Product: T
A
=0 to 70°C, otherwise specified
Industrial Product: T
A
=-40 to 85°C, otherwise specified
2. Overshoot: V
CC
+3.0V in case of pulse width
≤
30ns
3. Undershoot: -3.0V in case of pulse width
≤
30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
V
OL
V
OH
I
SB
V
IN
=Vss to Vcc
CS=V
IH
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH
, Read
Cycle time=1µs, 100% duty, I
IO
=0mA
CS≤0.2V, V
IN
≥0.2V
or V
IN
≥Vcc-0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
Test Conditions
Min
-1
-1
-
-
-
-
2.4
-
K6T4008C1C-L
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
1
1
10
8
55
0.4
-
3
80
20
100
30
Unit
µA
µA
mA
mA
mA
V
V
mA
I
OL
=2.1mA
I
OH
=-1.0mA
CS=V
IH
, Other inputs = V
IL
or V
IH
Standby Current(CMOS)
I
SB1
CS≥Vcc-0.2V, Other inputs=0~Vcc
K6T4008C1C-B
K6T4008C1C-P
K6T4008C1C-F
µA
4
Revision 1.0
April 1999
K6T4008C1C Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): C
L
=100pF+1TTL
C
L
=50pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(Vcc=4.5~5.5V, Commercial product:T
A
=0 to 70°C, Industrial product:T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
25
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
V
DR
Test Condition
CS≥Vcc-0.2V
K6T4008C1C-L
Min
2.0
-
-
-
-
0
5
Typ
-
-
-
-
-
-
-
Max
5.5
40
15
50
20
-
-
Unit
V
Data retention current
I
DR
Vcc=3.0V, CS≥Vcc-0.2V
K6T4008C1C-B
K6T4008C1C-P
K6T4008C1C-F
µA
Data retention set-up time
Recovery time
t
SDR
t
RDR
See data retention waveform
ms
5
Revision 1.0
April 1999
