K7A163600A
K7A163200A
K7A161800A
Document Title
512Kx36/x32 & 1Mx18 Synchronous SRAM
512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
Initial draft
1. Add JTAG Scan Order
1. Add x32 org and industrial temperature .
2. Add 165FBGA package
1. Speed Bin Merge
From K7A1636(32/18)09A to K7A1636(32/18)00A
2. AC parameter change
tOH(min)/tHZC(min) from 0.8 to 1.5 at -25
tOH(min)/tHZC(min) from 1.0 to 1.5 at -22
tOH(min)/tHZC(min) from 1.0 to 1.5 at -20
1. Final spec release
1. Release Icc.
part #
-25
-22
-20
-16
-14
From
440
400
370
340
280
To
470
430
400
350
290
April 04. 2003
Final
Draft Date
Feb. 23. 2001
May. 10. 2001
Aug. 31. 2001
Dec. 26. 2001
Remark
Preliminary
Preliminary
Preliminary
Preliminary
1.0
2.0
May. 10. 2002
May. 22. 2002
Final
Final
2.1
1. Delete 119BGA package.
2. Correct the Ball Size of 165 FBGA.
-1-
April 2003
Rev 2.1
K7A163600A
K7A163200A
K7A161800A
512Kx36/x32 & 1Mx18 Synchronous SRAM
16Mb SB/SPB Synchronous SRAM Ordering Information
Org.
Part Number
Mode
VDD
Speed
SB ; Access Time(ns)
SPB ; Cycle Time(MHz)
6.5/7.5/8.5ns
138MHz
250/225/200/167/138MHz
250/225/200/167/138MHz
6.5/7.5/8.5ns
138MHz
250/225/200/167/138MHz
250/225/200/167/138MHz
6.5/7.5/8.5ns
138MHz
250/225/200/167/138MHz
250/225/200/167/138MHz
Q : 100TQFP
F : 165FBGA
C
(Commercial
Temperature
Range)
PKG
Temp
K7B161825A-Q(F)C(I)65/75/85
1Mx18
K7A161880A-QC(I)14
K7A161800A-Q(F)C(I)25/22/20/16/14
K7A161801A-QC(I)25/22/20/16/14
K7B163225A-QC(I)65/75/85
512Kx32 K7A163280A-QC(I)14
K7A163200A-QC(I)25/22/20/16/14
K7A163201A-QC(I)25/22/20/16/14
K7B163625A-Q(F)C(I)65/75/85
512Kx36
K7A163680A-QC(I)14
K7A163600A-Q(F)C(I)25/22/20/16/14
K7A163601A-QC(I)25/22/20/16/14
SB
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
SB
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
SB
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
3.3
1.8
3.3
3.3
3.3
1.8
3.3
3.3
3.3
1.8
3.3
3.3
I
(Industrial
Temperature
Range)
NOTE :
119BGA is only supported with K7A163600A - HC16 and K7B163625A - HC75.
-2-
April 2003
Rev 2.1
K7A163600A
K7A163200A
K7A161800A
512Kx36/x32 & 1Mx18 Synchronous SRAM
512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A163600A , K7A163200A and K7A161800A are
18,874,368-bit Synchronous Static Random Access Mem-
ory designed for high performance second level cache of
Pentium and Power PC based System.
It is organized as 512K(1M) words of 36(32/18) bits and
integrates address and control registers, a 2-bit burst
address counter and added some new functions for high
performance cache RAM applications; GW, BW, LBO , ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by G W, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor (ADSP) or address status cache controller
(ADSC) inputs. Subsequent burst addresses are generated
internally in the system′s burst sequence and are con-
trolled by the burst address advance(ADV ) input.
LBO pin is DC operated and determines burst sequence
(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A163600A , K7A163200A and K7A161800A are
fabricated using SAMSUNG′s high performance CMOS
technology and is available in a 100pin TQFP and
165FBGA package. Multiple power and ground pins are
utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
t
CYC
t
C D
t
OE
-25
4.0
2.6
2.6
-22
4.4
2.8
2.8
-20
5.0
3.1
3.1
-16
6.0
3.5
3.5
-14
7.2
4.0
4.0
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
A′
0
~A′
1
COUNTER
A
0
~A
1
A
0
~A
18
or A
0
~A
19
ADDRESS
REGISTER
A
2
~A
18
or A
2
~A
19
512Kx36/32 , 1Mx18
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
BW
W
Ex
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa,DQPb
-3-
April 2003
Rev 2.1
K7A163600A
K7A163200A
K7A161800A
PIN CONFIGURATION
(TOP VIEW)
512Kx36/x32 & 1Mx18 Synchronous SRAM
A DSC
A DSP
W Ed
W Eb
W Ea
W Ec
A DV
83
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
A
5
A
4
A
3
A
2
A
1
A
0
A
18
A
17
A
10
A
11
A
12
A
13
A
14
A
15
N.C.
N.C.
LBO
V
SS
PIN NAME
SYMBOL
A
0
- A
18
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~ c
7
DQd
0
~d
7
DQPa~P
d
or N.C
V
DDQ
V
SSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
15,41,65,91
17,40,67,90
14,16,38,39,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
32,33,34,35,36,37,42
43,44,45,46,47,48,49
50,81,82,99,100
ADV
Burst Address Advance
83
ADSP
Address Status Processor 84
ADSC
Address Status Controller 85
CLK
Clock
89
CS
1
Chip Select
98
CS
2
Chip Select
97
CS
2
Chip Select
92
WE x(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
GW
Global Write Enable
88
BW
Byte Write Enable
87
ZZ
Power Down Input
64
LBO
Burst Mode Control
31
V
DD
Output Power Supply
(3.3V or 2.5V)
Output Ground
A
16
50
NC/DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
NC/DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7A163600A(512Kx36)
K7A163200A(512Kx32)
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Note :
1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-4-
April 2003
Rev 2.1
K7A163600A
K7A163200A
K7A161800A
PIN CONFIGURATION
(TOP VIEW)
512Kx36/x32 & 1Mx18 Synchronous SRAM
ADS C
ADS P
WEb
WEa
N.C.
N.C.
ADV
83
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
A
5
A
4
A
3
A
2
A
1
A
0
A
19
A
18
A
11
A
12
A
13
A
14
A
15
A
16
N.C.
N.C.
LBO
V
SS
PIN NAME
SYMBOL
A
0
- A
19
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,42
43,44,45,46,47,48,49
50 80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29
30,38,39,51,52,53,56,57
66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
W Ex(x=a,b)
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
V
DD
DQa
0
~ a
7
DQb
0
~ b
7
DQPa, Pb
V
DDQ
V
SSQ
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
Note :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
0
DQb
1
V
SSQ
V
DDQ
DQb
2
DQb
3
N.C.
V
DD
N.C.
V
SS
DQb
4
DQb
5
V
DDQ
V
SSQ
DQb
6
DQb
7
DQPb
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7A161800A(1Mx18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQPa
DQa
7
DQa
6
V
SSQ
V
DDQ
DQa
5
DQa
4
V
SS
N.C.
V
DD
ZZ
DQa
3
DQa
2
V
DDQ
V
SSQ
DQa
1
DQa
0
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
April 2003
Rev 2.1
Altera SoC
