K7B203625B
K7B203225B
K7B201825B
Document Title
64Kx36/x32 & 128Kx18 Synchronous SRAM
64Kx36/x32 & 128Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No.
0.0
History
1. Initial draft
Draft Date
Jan. 17. 2002
Remark
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
2Mb SB/SPB Synchronous SRAM Ordering Information
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
6.5/7.5/8.0 ns
250/225/200/167/138 MHz
6.5/7.5/8.0 ns
250/225/200/167/138 MHz
6.5/7.5/8.0 ns
250/225/200/167/138 MHz
Q
(100TQFP)
C
(Commercial
Temperature
Range)
I:
(Industrial
Temperature
PKG
Temp
128Kx18
K7B201825B-QC(I)65/75/80
K7A201800B-QC(I)25/22/20/16/14
SB
SPB(2E1D)
SB
SPB(2E1D)
SB
SPB(2E1D)
3.3
3.3
3.3
3.3
3.3
3.3
64Kx32
K7B203225B-QC(I)65/75/80
K7A203200B-QC(I)25/22/20/16/14
64Kx36
K7B203625B-QC(I)65/75/80
K7A203600B-QC(I)25/22/20/16/14
-2-
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
64Kx36/x32 & 128Kx18-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7B203625B, K7B203225B and K7B201825B are
2,359,296 bits Synchronous Static Random Access Memory
designed to support zero wait state performance for advanced
Pentium/Power PC based system. And with CS
1
high, ADSP is
blocked to control signals.
It can be organized as 64K(128K) words of 36(32/18) bits. And
it integrates address and control registers, a 2-bit burst address
counter and high output drive circuitry onto a single integrated
circuit for reduced components counts implementation of high
performance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B203625B, K7B203225B and K7B201825B are imple-
mented with SAMSUNG′s high performance CMOS technology
and is available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -65 -75 -80 Unit
t
CYC
t
CD
t
OE
7.5 8.5 10
6.5 7.5 8.0
3.5 3.5 4.0
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
A′0~A′1
COUNTER
A0~A1
64Kx36/32 , 128Kx18
MEMORY
ARRAY
ADSP
A0~A15
or A0~A16
ADDRESS
REGISTER
A2~A15
or A2~A16
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
DATA-IN
REGISTER
CONTROL
REGISTER
or DQa0 ~ DQb7
DQPa ~ DQPb
CONTROL
LOGIC
OUTPUT
BUFFER
36/32 or 18
-3-
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
PIN CONFIGURATION
(TOP VIEW)
64Kx36/x32 & 128Kx18 Synchronous SRAM
ADSC
ADSP
WEd
WEb
WEa
WEc
ADV
83
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
V
SS
LBO
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
11
A
12
A
13
A
14
N.C.
N.C.
N.C.
N.C.
A
15
PIN NAME
SYMBOL
A
0
- A
15
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
15,41,65,91
17,40,67,90
14,16,38,39,42,43,50,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
32,33,34,35,36,37
44,45,46,47,48,49
81,82,99,100
Burst Address Advance
83
Address Status Processor 84
Address Status Controller 85
Clock
89
Chip Select
98
Chip Select
97
Chip Select
92
Byte Write Inputs
93,94,95,96
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
86
88
87
64
31
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx
(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
DQa0~a7 Data Inputs/Outputs
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
VDDQ
VSSQ
Output Power Supply
(2.5V or 3.3V)
Output Ground
N.C.
50
DQPc/NC
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7B203625B(64Kx36)
K7B203225B(64Kx32)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
-4-
Jan 2002
Rev 0.0
K7B203625B
K7B203225B
K7B201825B
PIN CONFIGURATION
(TOP VIEW)
64Kx36/x32 & 128Kx18 Synchronous SRAM
ADSC
ADSP
WEb
WEa
ADV
83
N.C.
N.C.
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
V
SS
N.C.
N.C.
PIN NAME
SYMBOL
A
0
- A
16
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49,
80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,43,50,51,52,
53,56,57,66,75,78,79,95,
96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx
(x=a,b)
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
DQa
0
~a
7
DQb
0
~b
7
DQPa, Pb
V
DDQ
V
SSQ
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
11
A
12
A
13
A
14
A
15
LBO
A
16
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
0
DQb
1
V
SSQ
V
DDQ
DQb
2
DQb
3
N.C.
V
DD
N.C.
V
SS
DQb
4
DQb
5
V
DDQ
V
SSQ
DQb
6
DQb
7
DQPb
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7B201825B(128Kx18)
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQPa
DQa
7
DQa
6
V
SSQ
V
DDQ
DQa
5
DQa
4
V
SS
N.C.
V
DD
ZZ
DQa
3
DQa
2
V
DDQ
V
SSQ
DQa
1
DQa
0
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
-5-
Jan 2002
Rev 0.0
