K7M323625M
K7M321825M
Document Title
1Mx36 & 2Mx18 Flow-Through NtRAM
TM
1Mx36 & 2Mx18-Bit Flow Through NtRAM
TM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
1. Initial document.
1. Add 165FBGA package
1. Update JTAG scan order
1. Change pin out for 165FBGA
- x18/x36 ; 11B => from A to NC , 2R ==> from NC to A
1. Insert pin at JTAG scan order of 165FBGA in connection with
pin out change
- x18/x36 ; insert Pin ID of 2R to BIT number of 69
1. Add Icc, Isb, Isb1 and Isb2 values.
1. Final datasheet release.
1. Change the Stand-by current (Isb)
Before
After
Isb - 65 : 100
140
- 75 :
90
130
- 85 :
80
130
Isb1
:
90
110
Isb2
:
80
100
Draft Date
May. 10. 2001
Aug. 29. 2001
Dec. 03. 2001
Feb. 14. 2002
Remark
Preliminary
Preliminary
Preliminary
Preliminary
0.4
Apr. 20. 2002
Preliminary
0.5
1.0
1.1
May. 10. 2002
Sep. 26. 2002
Oct. 17. 2003
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Oct. 2003
Rev 1.1
K7M323625M
K7M321825M
1Mx36 & 2Mx18 Flow-Through NtRAM
TM
32Mb NtRAM(Flow Through / Pipelined) , Double Late Write RAM x72 Ordering Informa
tion
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
6.5/7.5/8.5ns
250/225/200/167/150/133MHz
250/225/200/167/150/133MHz
6.5/7.5/8.5ns
250/225/200/167/150/133MHz
250/225/200/167/150/133MHz
250/200/167MHz
H : 209BGA
Q:100TQFP
H:119BGA
F:165FBGA
C
(Commercial
Temperature
Range)
PKG
Temp
K7M321825M-Q(H/F)C65/75/85
2Mx18 K7N321801M-Q(H/F)C25/22/20/16/15/13
K7N321845M-Q(H/F)C25/22/20/16/15/13
K7M323625M-Q(H/F)C65/75/85
1Mx36 K7N323601M-Q(H/F)C25/22/20/16/15/13
K7N323645M-Q(H/F)C25/22/20/16/15/13
512Kx72 K7N327245M-HC25/20/16
FlowThrough
Pipelined
Pipelined
FlowThrough
Pipelined
Pipelined
Pipelined
(Normal Type)
3.3
3.3
2.5
3.3
3.3
2.5
2.5
-2-
Oct. 2003
Rev 1.1
K7M323625M
K7M321825M
1Mx36 & 2Mx18 Flow-Through NtRAM
TM
1Mx36 & 2Mx18-Bit Flow Through NtRAM
TM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
• 165FBGA(11x15 ball aray) with body size of 15mmx17mm.
GENERAL DESCRIPTION
The K7M323625M and K7M321825M are 37,748,736-bits Syn-
chronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M323625M and K7M321825M are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP, 119BGA and 165FBGA packages. Multi-
ple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -65
t
CYC
t
CD
t
OE
7.5
6.5
3.5
-75
8.5
7.5
3.5
-85 Unit
10
8.5
4.0
ns
ns
ns
LOGIC BLOCK DIAGRAM
LBO
A [0:19]or
A [0:20]
ADDRESS
REGISTER
A
2
~A
19
or A
2
~A
20
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
1Mx36 , 2Mx18
MEMORY
ARRAY
CLK
CKE
K
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
CONTROL
LOGIC
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
CONTROL
REGISTER
CONTROL
LOGIC
BUFFER
36 or 18
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
-3-
Oct. 2003
Rev 1.1
K7M323625M
K7M321825M
PIN CONFIGURATION
(TOP VIEW)
BWd
BWb
1Mx36 & 2Mx18 Flow-Through NtRAM
TM
BWa
BWc
CK E
ADV
CLK
CS
1
CS
2
CS
2
V
DD
V
SS
WE
A
18
A
17
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
19
A
10
A
11
A
12
A
13
A
14
A
15
PIN NAME
SYMBOL
A
0
- A
19
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~ c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
PIN NAME
TQFP PIN NO.
32,33,34,35,36,37,43
4445,46,47,48,49,50,
81,82,83,84,99,100
ADV
Address Advance/Load
85
WE
Read/Write Control Input 88
CLK
Clock
89
CKE
Clock Enable
87
CS
1
Chip Select
98
CS
2
Chip Select
97
CS
2
Chip Select
92
B Wx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
ZZ
Power Sleep Mode
64
LBO
Burst Mode Control
31
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
38,39,42
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
LBO
V
SS
-4-
A
16
50
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
Vss
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
81
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7M323625M(1Mx36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
SS
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
Oct. 2003
Rev 1.1
K7M323625M
K7M321825M
PIN CONFIGURATION
(TOP VIEW)
BWb
1Mx36 & 2Mx18 Flow-Through NtRAM
TM
BWa
CK E
N.C.
ADV
CS
2
N.C.
CLK
CS
1
CS
2
V
DD
V
SS
WE
A
19
A
18
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
20
A
11
A
12
A
13
A
14
A
15
A
16
PIN NAME
SYMBOL
A
0
- A
20
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
15,16,41,65,91
14,17,40,66,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,51,52,53,
56,57,75,78,79,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
32,33,34,35,36,37,43
44,45,46,47,48,49,50,
80,81,82,83,84,99,100
ADV
Address Advance/Load
85
WE
Read/Write Control Input 88
CLK
Clock
89
CKE
Clock Enable
87
CS
1
Chip Select
98
CS
2
Chip Select
97
CS
2
Chip Select
92
BW x(x=a,b) Byte Write Inputs
93,94
OE
Output Enable
86
ZZ
Power Sleep Mode
64
LBO
Burst Mode Control
31
LBO
V
SS
DQa
0
~a
8
DQb
0
~b
8
Data Inputs/Outputs
Data Inputs/Outputs
V
DDQ
V
SSQ
Output Power Supply
(2.5V or 3.3V)
Output Ground
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
SS
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7M321825M(2Mx18)
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
SS
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Notes :
1. A and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
0
-5-
Oct. 2003
Rev 1.1
模拟与混合信号
