K8A3215ET(B)E
NOR FLASH MEMORY
32Mb E-die NOR Specification
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.1
September, 2006
K8A3215ET(B)E
NOR FLASH MEMORY
Document Title
32M Bit (2M x16) Synchronous Burst , Multi Bank NOR Flash Memory
Revision History
Revision No. History
0.0
0.5
0.6
Initial Issue
Preliminary issue
Draft Date
July 15, 2005
Remark
Advance
December 21, 2005 Preliminary
Preliminary
tAVDH is changed to 2ns at all frequency
February 07, 2006
Remove tAVDP, tAAVDS, tAAVDH, tWEA
Add tAVDCS and tAVDCH to 0ns
tAS is changed to 0ns, tAH is changed to 50ns, tCS is changed to 5ns
tCH is changed to 5ns
Specification is finalized
"Asynchronous mode may not support read following four sequential
invalid read condition within 200ns." is added
August 24, 2006
September 08, 2006
1.0
1.1
2
Revision 1.1
September, 2006
K8A3215ET(B)E
FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 2,097,152 x 16 bit ( Word Mode Only)
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (2Mb Partition)
•
OTP Block : Extra 256Byte block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time :
90ns (54MHz) / 80ns (66MHz)
- Synchronous Random Access Time :
88.5ns (54MHz) / 70ns (66MHz)
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
•
Block Architecture
- Eight 4Kword blocks and sixty three 32Kword blocks
- Bank 0 contains eight 4 Kword blocks and three 32Kword
blocks
- Bank 1 ~ Bank 15 contain sixty 32Kword blocks
•
Reduce program time using the V
PP
•
Support Single & Quad word accelerate program
•
Power Consumption (Typical value, C
L
=30pF)
- Burst Access Current : 30mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode : 15uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring
RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
100K Program/Erase Cycles Minimum
•
Data Retention : 10 years
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Package : TBD
NOR FLASH MEMORY
32M Bit (2M x16) Synchronous Burst , Multi Bank NOR Flash Memory
GENERAL DESCRIPTION
The K8A3215E featuring single 1.8V power supply is a 32Mbit
Burst Multi Bank Flash Memory organized as 2Mbx16. The
memory architecture of the device is designed to divide its
memory arrays into 71 blocks with independent hardware pro-
tection. This block architecture provides highly flexible erase
and program capability. The K8A3215E NOR Flash consists of
sixteen banks. This device is capable of reading data from one
bank while programming or erasing in the other bank.
Regarding read access time, the K8A3215E provides an 14.5ns
burst access time and an 90ns initial access time at 54MHz. At
66MHz, the K8A3215E provides an 11ns burst access time and
70ns initial access time. The device performs a program opera-
tion in units of Single 16 bits (word) and an erase operation in
units of a block. Single or multiple blocks can be erased. The
block erase operation is completed within typically 0.7 sec. The
device requires 15mA as program/erase current in the
extended temperature ranges.
The K8A3215E NOR Flash Memory is created by using Sam-
sung's advanced CMOS process technology.
PIN DESCRIPTION
Pin Name
A0 - A20
DQ0 - DQ15
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
Vcc
V
SS
Pin Function
Address Inputs
Data input/output
Chip Enable
Output Enable
Hardware Reset Pin
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Power Supply
Ground
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
3
Revision 1.1
September, 2006
K8A3215ET(B)E
Package TYPE
NOR FLASH MEMORY
TBD
FUNCTIONAL BLOCK DIAGRAM
Bank 0
Address
Vcc
Vss
Vpp
CLK
CE
OE
WE
WP
RESET
RDY
AVD
I/O
Interface
&
Bank
Control
Bank 1
Address
X
Dec
Bank 0
Cell Array
Y Dec
Latch &
Control
Y Dec
X
Dec
Bank 1
Cell Array
Latch &
Control
Bank 15
Address
X
Dec
Bank 15
Cell Array
Y Dec
A0~A20
DQ0~
DQ15
Erase
Control
Block
Inform
Program
Control
Latch &
Control
High
Voltage
Gen.
4
Revision 1.1
September, 2006
K8A3215ET(B)E
ORDERING INFORMATION
NOR FLASH MEMORY
K 8 A 32 1 5 E T E - D E 7C
Samsung
NOR Flash Memory
Device Type
De-Multiplexed Burst
Access Time
Refer to Table 1
Operating Temperature Range
C = Commercial Temp. (0
°C
to 70
°C)
E = Extended Temp. (-25
°C
to 85
°C)
Package
F : FBGA
D : FBGA(Lead Free)
Version
6th Generation
Block Architecture
T = Top Boot Block, B = Bottom Boot Block
Density
32Mbits
Organization
x16 Organization
Operating Voltage Range
1.7 V to 1.95V
Table 1. PRODUCT LINE-UP
K8A3215E
Synchronous/Burst
Speed Option
Max. Initial Access Time (t
IAA,
ns)
V
CC
=1.7V-1.95V Max. Burst Access Time (t
BA,
ns)
Max. OE Access Time (t
OE,
ns)
7B
(54MHz)
88.5
14.5
20
7C
(66MHz)
70
11
20
Asynchronous
Speed Option
Max Access Time (t
AA,
ns)
Max CE Access Time (t
CE,
ns)
Max OE Access Time (t
OE,
ns)
7B
7C
(54MHz) (66MHz)
90
90
20
80
80
20
Table 2. K8A3215E DEVICE BANK DIVISIONS
Bank 0
Mbit
2 Mbit
Block Sizes
Eight 4Kwords,
Three 32Kwords
Mbit
30 Mbit
Bank 1 ~ Bank 15
Block Sizes
Sixty 32Kwords
5
Revision 1.1
September, 2006
