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K8C54(55)15ET(B)M

NOR FLASH MEMORY

256Mb M-die MLC NOR Specification

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUB-

JECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFOR-

MATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications

where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any

governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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Revision 1.5

December, 2006

K8C54(55)15ET(B)M

Document Title

NOR FLASH MEMORY

256M Bit (16M x16) Sync Burst , Multi Bank MLC NOR Flash Memory

Revision History

Revision No.

0.0

0.5

0.6

History

Initial

Preliminary

- Added Burst Access time(11ns@66Mhz, 9ns@83Mhz)

- Correct the Active Write Current (typ.15mA, max.30mA --> typ.25mA,

max.40mA)

- Correct tBDH(Data Hold Time from Next Clock Cycle) from

4ns(@66MHz), 2.25ns(@108MHz), 1.5ns(@133MHz) to

3ns(@66MHz), 2ns(@108MHz), 2ns(@133MHz)

- Correct tRDYA(Clock to RDY Setup Time) from 8ns(@83Mhz) to

9ns(@83MHz)

- Correct tRDYS(RDY setup to Clock) from 4ns(@66MHz),

2.25ns(@108MHz), 1.5ns(@133MHz) to 3ns(@66MHz),

2ns(@108MHz), 2ns(@133MHz)

- Correct typo

- Add Ordering Information for Density

56 : 256Mb for 66/83MHz, 57 : 267Mb for 108/133Mhz

- Add Product Classification Table (Table 1-1)

- Change tAVDH(AVD Hold Time from CLK) from 6ns(@66MHz),

5ns(@83MHz) to 2ns(@66/83MHz)

- Delete tOH(

Output Hold Time from Address, CE or OE ) from Asynchronous

Read parameter

Draft Date

April 1, 2005

September 1, 2005

November 7, 2005

Remark

Advance

Preliminary

0.7

December 7, 2005

Preliminary

0.8

- CFI note is added (Max Operation frequency : Data 53H is in 66/83Mhz

part

- tAVDO is deleted

- Specification is finalized

April 04,2006

Preliminary

1.0

April 25,2006

1.1

Active Asynchronous read Current(@1Mhz) is changed

September 08,2006

3mA(typ.),5mA(max.) to 8mA(typ.), 10mA(max.)

'In erase/program suspend followed by resume operation, min. 200ns is

needed for checking the busy status' is added

Frequency information is added to Programmable Wait State at Burst

Mode Configuration Register Table.

"Asynchronous mode may not support read following four sequential invalid

read condition within 200ns." is added

Correct typo

October 17, 2006

In write buffer programming part, "And from the third cycle to the last cycle

of Write to Buffer command is also required when using Write-Buffer-Pro-

gramming features in Unlock Bypass mode." is added.

2 AC parameters are changed.

At 66MHz and 83MHz, change tBDH form 3ns to 4ns.

At 108MHz and 133MHz, change tBDH form 2ns to 3ns.

Change tCES form 6ns to 5ns at all frequency regions.

Add Synchronous Read Mode Setting by A19

Change tCES form 5ns to 4.5ns at all frequency regions.

Registered as a new part ID, K8C54(55)15ET(B)M.

Ordering Information is updated.

October 19, 2006

1.2

1.3

1.4

1.5

December 04, 2006

December 27, 2006

-2-

Revision 1.5

December, 2006

K8C54(55)15ET(B)M

Table of Contents

FEATURES 1

NOR FLASH MEMORY

GENERAL DESCRIPTION ............................................................................................................................................... 1

PIN DESCRIPTION .......................................................................................................................................................... 2

Pin Configuration .............................................................................................................................................................. 3

Ball FBGA VIEW .............................................................................................................................................................. 4

FUNCTIONAL BLOCK DIAGRAM.................................................................................................................................... 4

ORDERING INFORMATION ............................................................................................................................................ 5

PRODUCT INSTRUCTION .............................................................................................................................................. 18

COMMAND DEFINITIONS ............................................................................................................................................... 19

DEVICE OPERATION ...................................................................................................................................................... 21

Read Mode ................................................................................................................................................................. 21

Asynchronous Read Mode .................................................................................................................................... 21

Synchronous (Burst) Read Mode .......................................................................................................................... 21

Continuous Linear Burst Read......................................................................................................................... 21

8-, 16-Word Linear Burst Read .................................................................................................................. 21

Programmable Wait State .......................................................................................................................... 22

Handshaking .............................................................................................................................................. 22

Set Burst Mode Configuration Register....................................................................................................................... 22

Programmable Wait State Configuration.................................................................................................... 23

Burst Read Mode Setting........................................................................................................................... 23

RDY Configuration ..................................................................................................................................... 23

Autoselect Mode ......................................................................................................................................................... 23

Standby Mode ............................................................................................................................................................. 23

Autosleep Mode .......................................................................................................................................................... 24

Output Disable Mode .................................................................................................................................................. 24

Block Protection & Unprotection ................................................................................................................................. 24

Hardware Reset .......................................................................................................................................................... 24

Software Reset............................................................................................................................................................ 24

Program ...................................................................................................................................................................... 24

Accelerated Program............................................................................................................................................. 25

Write Buffer Programming..................................................................................................................................... 25

Accelerated Write Buffer Programming................................................................................................................. 25

Chip Erase .................................................................................................................................................................. 26

Block Erase ................................................................................................................................................................. 26

Unlock Bypass ............................................................................................................................................................ 26

Erase Suspend / Resume ........................................................................................................................................... 26

Program Suspend / Resume....................................................................................................................................... 27

Read While Write Operation ....................................................................................................................................... 27

OTP Block Region....................................................................................................................................................... 27

Low VCC Write Inhibit ................................................................................................................................................. 27

Write Pulse “Glitch” Protection .................................................................................................................................... 27

Logical Inhibit .............................................................................................................................................................. 27

Deep Power Down ...................................................................................................................................................... 27

FLASH MEMORY STATUS FLAGS ................................................................................................................................. 29

DQ7 : Data Polling ...................................................................................................................................................... 29

DQ6 : Toggle Bit.......................................................................................................................................................... 29

DQ5 : Exceed Timing Limits........................................................................................................................................ 29

DQ3 : Block Erase Timer ............................................................................................................................................ 30

DQ2 : Toggle Bit 2....................................................................................................................................................... 30

DQ1 : Buffer Program Abort Indicator ......................................................................................................................... 30

RDY: Ready ................................................................................................................................................................ 30

Commom Flash Memory Interface ................................................................................................................................... 31

ABSOLUTE MAXIMUM RATINGS ................................................................................................................................... 33

Revision 1.5

November 2006

-1-

K8C54(55)15ET(B)M

Table of Contents

NOR FLASH MEMORY

RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND ) ................................................................ 34

DC CHRACTERISTICS .................................................................................................................................................... 34

CAPACITANCE(TA = 25 ×C, VCC = 1.8V, f = 1.0MHz)................................................................................................... 34

AC TEST CONDITION ..................................................................................................................................................... 35

AC CHARACTERISTICS................................................................................................................................................. 35

Synchronous/Burst Read

..................................................................................................................................... 35

Asynchronous Read.................................................................................................................................................... 38

Erase/Program Operation ........................................................................................................................................... 41

Erase/Program Performance

............................................................................................................................... 42

Crossing of First Word Boundary in Burst Read Mode..................................................................................................... 47

Case1 : Start from "16N" address group..................................................................................................................... 48

Case2 : Start from "16N+2" address group................................................................................................................. 48

Case3 : Start from "16N+3" address group................................................................................................................. 49

Case4 : Start from "16N+15" address group............................................................................................................... 49

Case5 : Start from "16N+15" address group............................................................................................................... 50

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Revision 1.5

November 2006

K8C54(55)15ET(B)M

NOR FLASH MEMORY

256M Bit (16M x16) Synch Burst , Multi Bank MLC NOR Flash Memory

FEATURES

•

Single Voltage, 1.7V to 1.95V for Read and Write operations

•

Organization

- 16,777,216 x 16 bit ( Word Mode Only)

•

Read While Program/Erase Operation

•

Multiple Bank Architecture

- 16 Banks (16Mb Partition)

•

OTP Block : Extra 512-Word block

•

Read Access Time (@ C

=30pF)

- Asynchronous Random Access Time : 100ns

- Synchronous Random Access Time :100ns

- Burst Access Time :

11ns(66Mhz) / 9ns(83Mhz) / 7ns (108MHz) / 6ns (133MHz)

•

Burst Length :

- Continuous Linear Burst

- Linear Burst : 8-word & 16-word with No-wrap & Wrap

•

Block Architecture

- Four 16Kword blocks and two hundreds fifty-five 64Kword blocks

- Bank 0 contains four 16 Kword blocks and fifteen 64Kword blocks

- Bank 1 ~ Bank 15 contain two hundred forty 64Kword blocks

•

Reduce program time using the V

•

Support 32 words Buffer Program

•

Power Consumption (Typical value, C

=30pF)

- 16-word Synchronous Read Current : 35mA at 133MHz

- Program/Erase Current : 25mA

- Read While Program/Erase Current : 45mA

- Standby Mode/Auto Sleep Mode : 30uA

•

Block Protection/Unprotection

- Using the software command sequence

- Last two boot blocks are protected by WP=V

- All blocks are protected by V

•

Handshaking Feature

- Provides host system with minimum latency by monitoring RDY

•

Erase Suspend/Resume

•

Program Suspend/Resume

•

Unlock Bypass Program/Erase

•

Hardware Reset (RESET)

•

Deep Power Down Mode

•

Data Polling and Toggle Bits

- Provides a software method of detecting the status of program

or erase completion

•

Endurance

100K Program/Erase Cycles Minimum

•

Data Retention : 10 years

•

Extended Temperature : -25°C ~ 85°C

•

Support Common Flash Memory Interface

•

Low Vcc Write Inhibit

•

Package : 167-Ball FBGA type, 10.5mm x 14.0mm

0.8mm ball pitch

1.4mm (Max.) Thickness

GENERAL DEK8C54SCRIPTION

The K8C54(55)15E featuring single 1.8V power supply is a 256Mbit Burst Multi Bank Flash Memory organized as 16Mx16. The memory

architecture of the device is designed to divide itsK8C55 memory arrays into 259 blocks with independent hardware protection. This block

architecture provides highly flexible erase and program capability. The K8C54(55)15E NOR Flash consists of sixteen banks. This device is

capable of reading data from one bank while programming or erasing in the other bank.

Regarding read access time, the K8C5415E provides an 11ns burst access time and an 100ns initial access time at 66MHz.

At 83Mhz, the K8C5415E provides an 9ns burst access time and an 100ns initial access time at 83MHz. At 108Mhz, the K8C5515E provides

an 7ns burst access time and an 100ns initial access time at 83MHz. At 133MHz, the K8C5515E provides an 6ns burst access time and 100ns

initial access time. The device performs a program operation in units of 16 bits (Word) and erases in units of a block. Single or multiple blocks

can be erased. The block erase operation is completed within typically 0.6sec. The device requires 25mA as program/erase current in the

extended temperature ranges.

The K8C54(55)15E NOR Flash Memory is created by using Samsung's advanced CMOS process technology.

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Revision 1.5

December 2006

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