K8P2815UQB
FLASH MEMORY
128Mb B-die Page NOR Specification
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.3
June 2007
K8P2815UQB
FLASH MEMORY
Document Title
128M Bit (8M x16) Page Mode / Multi-Bank NOR Flash Memory
Revision History
Revision No. History
0.0
Initial draft
Draft Date
July 22, 2005
Remark
Target
Information
0.1
- Added OTP indicator bit in autoselect table
- Define customer and factory OTP area
- OTP Enter and Exit command is changed
- OTP protect bit program and status command is added
- Page read current is changed to 10mA(Typ)
- Die version is changed
(K8P2815UQM to K8P2815UQC)
- WP has an internal pullup, when unconnected
- Correct pin configuration of 56 Pin TSOP
- CFI information at the address 28h is changed from 0002h to 0001h
(Flash Device Interface description)
- Add read cycles to read Device ID
- Correct typo
- Add note for speed option in case of using 1.65~1.95V VIO
- Correct description of indicator bit for OTP
- Correct the extended temp.(-25~85°C)
- Die version is changed C to B
- Voltage range for MCP is added(2.7~3.1V)
- Correct typo
- Standby current value is changed 5uA(typ),18uA(max) to
15uA(typ),30uA(max)
- Autosleep current value is changed 5uA(typ),18uA(max) to
15uA(typ),30uA(max)
- Correct typo
- Bank address is added on the 3rd cycle of DBY status command
address
- 64FBGA Package is added
- Industial temp. is added
- Vih is changed 2.0 to 2.2
- 56TSOP pin is revised
-Accelerated Program Time is changed from 4us to 6us.
-Accelerated Quad Word Program Time is changed from 1.2us to
1.5us.
-TSOP Package is removed.
-64FBGA with 1.0mm BallPitch is added.
-64 Ball Fine-pitch BGA 8x11.6mm is deleted.
- Group block protect time : 100us --> 120us
- Group block unprotect time : 1.2ms --> 3ms
In Figure 8. Block Group Protection & Unprotection Algorithms &
Block Group Protect & Unprotect Operations timing
- Specification is finalized.
2
December 17,2005 Target
Information
0.2
January 20, 2006
Target
Information
0.3
March 17, 2006
Target
Information
0.4
March 21, 2006
Target
Information
Target
Information
Target
Information
Target
Information
0.5
March 28, 2006
0.6
April 28, 2006
0.7
May 17,2006
0.8
September 7,2006
Target
Information
0.9
0.9.1
0.9.2
Target
Information
November 10,2006 Target
Information
November 13,2006 Target
Information
October 09,2006
0.9.3
0.9.4
1.0
November 14,2006 Target
Information
Target
January 09,2007
Information
February 08, 2007 Target
Information
Revision 1.3
June 2007
K8P2815UQB
Revision No. History
1.1
1.2
- Package Hight is changed from 1.3
±0.10
to 1.2
±0.10.
- "#OE or #CE should be toggled in each toggle bit status read." is
added in DQ2 & DQ6 toggle bit.
- Package 'E' is added in ordering information.
- Fast access time 55ns is deleted.
- Absolute maximum ratings
All other pins value is changed -0.5 to 2.5 to -0.5 to Vcc + 0.5.
FLASH MEMORY
Draft Date
February 15, 2007
April 23, 2007
Remark
1.3
June 25, 2007
3
Revision 1.3
June 2007
K8P2815UQB
FLASH MEMORY
128M Bit (8M x16) Page Mode / Multi-Bank NOR Flash Memory
FEATURES
•
Single Voltage, 2.7V to 3.6V for Read and Write operations
Voltage range of 2.7V to 3.1V valid for MCP product
•
Organization
8M x16 bit (Word mode Only)
•
Fast Read Access Time : 60ns
•
Page Mode Operation
8 Words Page access allows fast asychronous read
Page Read Access Time : 25ns
•
Read While Program/Erase Operation
•
Multiple Bank architectures (4 banks)
Bank 0: 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1: 48Mbit (32Kw x 96)
Bank 2: 48Mbit (32Kw x 96)
Bank 3: 16Mbit (4Kw x 8 and 32Kw x 31)
•
OTP Block : Extra 256 word
- 128word for factory and 128word for customer OTP
•
Power Consumption (typical value)
- Active Read Current : 45mA (@10MHz)
- Program/Erase Current : 17mA
- Read While Program or Read While Erase Current : 35mA
- Standby Mode/Auto Sleep Mode : 15uA
•
Support Single & Quad word accelerate program
•
WP/ACC input pin
- Allows special protection of two outermost boot blocks at V
IL
,
regardless of block protect status
- Removes special protection of two outermost boot block at V
IH,
the two blocks return to normal block protect status
- Accelerated Quadword Program time : 1.5us
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program
•
Hardware RESET Pin
•
Command Register Operation
•
Block Protection / Unprotection
•
Supports Common Flash Memory Interface
•
Industrial Temperature : -40°C to 85°C
•
Extended Temperature : -25°C to 85°C
•
Endurance : 100,000 Program/Erase Cycles Minimum
•
Data Retention : 10 years
•
Vio options at 1.8V and 3V I/O
•
Package options
- 80 Ball Fine-pitch BGA (11x8mm, 0.8mm Ball Pitch)
- 64 Ball FBGA (13x11mm, 1.0mm Ball Pitch)
GENERAL DESCRIPTION
The K8P2815UQB featuring single 3.0V power supply, is an
128Mbit NOR-type Flash Memory organized as 8M x16. The
memory architecture of the device is designed to divide its
memory arrays into 270 blocks with independent hardware pro-
tection. This block architecture provides highly flexible erase
and program capability. The K8P2815UQB NOR Flash consists
of four banks. This device is capable of reading data from one
bank while programming or erasing in the other banks.
The K8P2815UQB offers fast page access time of 25~30ns with
random access time of 60~70ns. The device′s fast access
times allow high speed microprocessors to operate without wait
states. The device performs a program operation in unit of 16
bits (Word) and erases in units of a block. Single or multiple
blocks can be erased. The block erase operation is completed
within typically 0.7 sec. The device requires 15mA as program/
erase current in the commercial and industrial temperature
ranges.
The K8P2815UQB NOR Flash Memory is created by using
Samsung's advanced CMOS process technology. This device is
available in 80/64 ball FBGA. The device is compatible with
EPROM applications to require high-density and cost-effective
non-volatile read/write storage solutions.
PIN DESCRIPTION
Pin Name
A0 - A22
DQ0 - DQ15
CE
OE
RESET
RY/BY
WE
WP/ACC
Vcc
V
SS
N.C
Address Inputs
Data Inputs / Outputs
Chip Enable
Output Enable
Hardware Reset Pin
Ready/Busy Output
Write Enable
Hardware Write Protection/Program Acceleration
Power Supply
Ground
No Connection
Pin Function
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
4
Revision 1.3
June 2007
K8P2815UQB
64 Ball FBGA TOP VIEW (BALL DOWN)
A
B
C
D
E
F
G
FLASH MEMORY
H
8
NC
A22
NC
VIO
Vss
NC
NC
NC
7
6
A13
A12
A14
A15
A16
NC
DQ15
Vss
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
5
WE
RESET
A21
A19
DQ5
DQ12
Vcc
DQ4
4
RY/BY
WP/ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
2
A3
A4
A2
A1
A0
CE
OE
Vss
1
NC
NC
NC
NC
NC
VIO
NC
NC
5
Revision 1.3
June 2007
