K8P2915UQB
FLASH MEMORY
128Mb B-die Page NOR Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.1
October, 2006
K8P2915UQB
FLASH MEMORY
Document Title
128M Bit (8M x16) Page Mode / Multi-Bank NOR Flash Memory
Revision History
Revision No. History
0.0
0.1
- Initial draft
- Autoselect code table is added
Draft Date
May 12, 2006
May 18,2006
Remark
Target
Information
Target
Information
Preliminary
0.5
- Bank address is added on the 3rd cycle of DBY status command
address
- Add 64 Ball FBGA Package type
- Specification is finalized
- Vih is changed 2.0 to 2.2V (min)
August 28,2006
1.0
1.1
September 14,2006
October 09,2006
2
Revision 1.1
October, 2006
K8P2915UQB
FLASH MEMORY
128M Bit (8M x16) Page Mode / Multi-Bank NOR Flash Memory
FEATURES
•
Single voltage : 2.7V ~ 3.6V for Read While Write operation
Voltage range of 2.7V to 3.1V valid for MCP product
•
Organization
8M x16 bit (Word mode Only)
•
Fast Read Access Time : 55ns
•
Page Mode Operation
8 Words Page access allows fast asychronous read
Page Read Access Time : 20ns
•
Dual Chip Enable inputs
- Two CE# inputs control selection of each half of the
memory space
•
Read While Program/Erase Operation
•
Multiple Bank architectures (4 banks)
- CE#1 controlled banks
Bank 1A : 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B : 48Mbit (32Kw x 96)
- CE#2 controlled banks
Bank 2A : 48Mbit (32Kw x 96)
Bank 2B : 16Mbit (4Kw x 8 and 32Kw x 31)
•
OTP Block : Extra 256 word
- 128word for factory and 128word for customer OTP
•
Power Consumption (typical value)
- Active Read Current : 45mA (@10MHz)
- Program/Erase Current : 17mA
- Read While Program or Read While Erase Current : 35mA
- Standby Mode/Auto Sleep Mode : 15uA
•
Support Single & Quad word accelerate program
•
WP/ACC input pin
- Allows special protection of two outermost boot blocks at V
IL
,
regardless of block protect status
- Removes special protection of two outermost boot block at V
IH,
the two blocks return to normal block protect status
- Reduce program time at V
HH
: 4us/word
- Accelerated Quadword Program time : 1.2us
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program
•
Hardware RESET Pin
•
Command Register Operation
•
Block Protection / Unprotection
•
Supports Common Flash Memory Interface
•
Extended Temperature : -25°C to 85°C
•
Endurance : 100,000 Program/Erase Cycles Minimum
•
Data Retention : 10 years
•
Vio options at 1.8V and 3V I/O
•
Package options
- 64 Ball Fine-pitch BGA (8x11.6mm)
- 80 Ball Fine-pitch BGA (11x8mm)
GENERAL DESCRIPTION
The K8P2915UQB featuring single 3.0V power supply, is an
128Mbit NOR-type Flash Memory organized as 8M x16. The
memory architecture of the device is designed to divide its
memory arrays into 270 blocks with independent hardware pro-
tection. This block architecture provides highly flexible erase
and program capability. The K8P2915UQB NOR Flash consists
of four banks. This device is capable of reading data from one
bank while programming or erasing in the other banks.
The K8P2915UQB offers fast page access time of 20~30ns with
random access time of 55~70ns. The device′s fast access
times allow high speed microprocessors to operate without wait
states. The device performs a program operation in unit of 16
bits (Word) and erases in units of a block. Single or multiple
blocks can be erased. The block erase operation is completed
within typically 0.7 sec. The device requires 15mA as program/
erase current in the commercial and industrial temperature
ranges.
The K8P2915UQB NOR Flash Memory is created by using
Samsung's advanced CMOS process technology. This device is
available in 80 ball FBGA and 64 ball FBGA. The device is com-
patible with EPROM applications to require high-density and
cost-effective non-volatile read/write storage solutions.
PIN DESCRIPTION
Pin Name
A0 - A21
DQ0 - DQ15
CE1
CE2
OE
RESET
RY/BY
WE
WP/ACC
Vcc
V
SS
N.C
Pin Function
Address Inputs
Data Inputs / Outputs
Chip Enable1
Chip Enable2
Output Enable
Hardware Reset Pin
Ready/Busy Output
Write Enable
Hardware Write Protection/Program
Acceleration
Power Supply
Ground
No Connection
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
3
Revision 1.1
October, 2006
K8P2915UQB
80 Ball FBGA TOP VIEW (BALL DOWN)
1
2
3
A
B
C
D
E
F
G
H
J
K
L
M
NC
NC
FLASH MEMORY
4
5
6
7
NC
8
NC
NC
NC
RY
/BY#
WP#/
ACC
A18
NC
NC
NC
A3
A7
WE#
RESET
#
A21
A9
A13
NC
NC
A4
A17
A8
A12
CE#2
NC
A2
A6
A10
A14
NC
NC
A1
A5
A20
A19
A11
A15
Vio
NC
A0
DQ0
DQ2
DQ5
DQ7
A16
Vss
Vio
CE#1
DQ8
DQ10
DQ12
DQ14
NC
NC
NC
OE#
DQ9
DQ11
Vcc
DQ13
DQ15
NC
NC
Vss
DQ1
DQ3
DQ4
DQ6
Vss
NC
NC
NC
NC
NC
NC
NC
NC
NC
4
Revision 1.1
October, 2006
K8P2915UQB
64 Ball FBGA TOP VIEW (BALL DOWN)
1
2
3
4
5
6
7
8
9
FLASH MEMORY
10
A
B
C
D
E
F
G
H
J
K
L
M
DNU
DNU
NC
NC
A7
RFU
WP/ACC
WE
A8
A11
A3
A6
RFU
Reset
RFU
A19
A12
A15
A2
A5
A18
RY/BY
A20
A9
A13
A21
A1
A4
A17
A10
A14
CEr2
A0
Vss
DQ1
DQ6
NC
A16
CEr1
OE
DQ9
DQ3
DQ4
DQ13
DQ15
NC
RFU
DQ0
DQ10
Vcc
RFU
DQ12
DQ7
Vss
DQ8
DQ2
DQ11
NC
DQ5
DQ14
NC
NC
DNU
DNU
FUNCTIONAL BLOCK DIAGRAM
Bank 1A
Address
Vcc
Vss
CE1
CE2
OE
WE
RESET
RY/BY
WP/ACC
A0~A21
DQ0~DQ15
Block
Inform
Erase
Control
Program
Control
5
High
Voltage
Gen.
I/O
Interface
&
Bank
Control
Bank 1B
Address
X
Dec
X
Dec
Bank 1A
Cell Array
Y Dec
Latch &
Control
Y Dec
Bank 1B
Cell Array
Latch &
Control
Bank 2B
Address
X
Dec
Bank 2B
Cell Array
Y Dec
Latch &
Control
Revision 1.1
October, 2006
