Rev. 1.3, May. 2010
K8P5516UZB
256Mb B-die NOR FLASH
56TSOP, 64FBGA, Page Mode
2.7V ~ 3.6V
datasheet
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K8P5516UZB-P(E)/I(C)(E)/4E
datasheet
History
Rev. 1.3
NOR FLASH MEMORY
Revision History
Revision No.
0.0
0.1
Initial draft
Description of Hardwre Protection in Figure 8: Enhanced Block Pro-
tection/Unprotection is changed from"A outermost block on both ends
of flash array locked" to "Highest or lowest block locked"
DC Characteristics Table is revised.
- "Read While Program Current"(I2) and "Read While Erase Cur-
rent"(I3) are deleted.
- "WP/ACC Input Leakage Current" is changed to "A9 Input Leakage
Current".
- "Active Write Current " is changed to " Vcc Active Read Current".
- "V
IO
Non-Active Output", I
IO
2 is added.
- "Voltage for WP/ACC Block Temporarily Unprotect and Program
Acceleration" is changed to "Voltage for Program Acceleration ".
- "Voltage for Autoselect and Temporary Sector Unprotect", V
ID
is
added.
FEATURE is revised.
- "Read While Program/Erase Operation" is deleted.
- "Read While Program or Read While Erase Current : 55mA " is
deleted.
Figure : Write Buffer Program Command Sequence is revised.
CFI Table is revised.
- Address 30H data changed from 0001H to 0002H.
- Address 34H data changed from 0004H to 0000H.
0.2
0.3
FEATURE is revised.
- 64Mbitx256 is changed to 64Kwordx256.
- 64FBGA Package Demension is added.
- Endurance is added.
- Indicator Bit Codes table description is corrected
-"The data is DQ6 = "1" for customer locked and DQ7 = "1" for factory
locked." is changed to " The DQ7 is "1" for factory locked."
- Device ID data is revised from 227EH, 2264H and 2260H to XX7EH,
XX64H and XX60H on Command Sequences(x8) table.
- Byte Mode Address is added to CFI table.
CFI Table is revised.
- Address 38H data changed from 0001H to 0000H.
- "Blocks must be unprotected before raising WP/ACC to V
HH
. " is
added to accelerated program operation.
- "When the WP/ACC pin is asserted as V
HH
, the device automatically
enters the Unlock Bypass mode, temporarily unprotecting any pro-
tected blocks, and reduces the program operation time." is changed
to "When the WP/ACC pin is asserted as V
HH
, the device automati-
cally enters the Unlock Bypass mode, and reduces the program oper-
ation time. "
- 64FBGA Package Demension is revised.
- Ordering Information is revised.
1.0
- Deleted speed code for 4C / 4D.
- AC parameter table for speed code 4C and 4D is deleted.
- Min. VIH DC value is changed from 2.0V to VCC x 0.7V.
- ICC6 is changed from Typ. 6mA and Max. 10mA to Typ. 10mA and
Max. 15mA
Dec. 11, 2008
Final
-
June 12, 2008
June 27, 2008
Target
Target
-
-
Draft Date
Mar.03,2008
May.15,2008
Remark
Target
Target
Editor
-
-
0.4
July 04,2008
Target
-
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K8P5516UZB-P(E)/I(C)(E)/4E
datasheet
Rev. 1.3
NOR FLASH MEMORY
Final
-
1.1
- NOTE is deleted. Related NOTE is below.
NOTE :
The device supports only 4E at VIO = 1.7~1.95V.
- Package dimension of 56-TSOP is revised.
Apr. 02, 2009
1.2
- Revised Hardware Sequence Flags Table.
- Deleted DQ6 as Customer OTP Lock information in 12. OTP Block
Region.
Jun. 02, 2009
Final
-
1.3
- Correct typo
May 12, 2010
Final
-
-3-
K8P5516UZB-P(E)/I(C)(E)/4E
datasheet
Rev. 1.3
NOR FLASH MEMORY
Table Of Contents
256Mb B-die NOR FLASH
1.0 FEATURES................................................................................................................................................................. 5
2.0 GENERAL DESCRIPTION ......................................................................................................................................... 5
3.0 PIN DESCRIPTION .................................................................................................................................................... 6
4.0 56TSOP PIN CONFIGURATION ................................................................................................................................ 7
5.0 64 Ball FBGA TOP VIEW (BALL DOWN) ................................................................................................................... 7
6.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 8
7.0 ORDERING INFORMATION ...................................................................................................................................... 9
8.0 PRODUCT INTRODUCTION...................................................................................................................................... 10
9.0 COMMAND DEFINITIONS ......................................................................................................................................... 11
10.0 DEVICE OPERATION .............................................................................................................................................. 16
10.1 Read Mode ............................................................................................................................................................ 16
10.2 Standby Mode ....................................................................................................................................................... 16
10.3 Output Disable....................................................................................................................................................... 16
10.4 Automatic Sleep Mode .......................................................................................................................................... 16
10.5 Autoselect Mode.................................................................................................................................................... 16
10.6 Write (Program/Erase) Mode................................................................................................................................. 17
10.6.1 Program .......................................................................................................................................................... 17
10.6.2 Writer Buffer Programming ............................................................................................................................. 18
10.6.3 Accelerated Program Operation...................................................................................................................... 19
10.6.4 Unlock Bypass ................................................................................................................................................ 20
10.6.5 Chip Erase ...................................................................................................................................................... 20
10.6.6 Block Erase ..................................................................................................................................................... 20
10.7 Erase Suspend / Resume...................................................................................................................................... 21
10.8 Program Suspend / Resume ................................................................................................................................. 21
10.9 Write Protect (WP)................................................................................................................................................. 22
10.10 Software Reset .................................................................................................................................................... 22
10.11 Hardware Reset................................................................................................................................................... 22
10.12 Power-up Protection ............................................................................................................................................ 23
10.13 Low Vcc Write Inhibit ........................................................................................................................................... 23
10.14 Write Pulse Glitch Protection............................................................................................................................... 23
10.15 Logical Inhibit....................................................................................................................................................... 23
11.0 COMMON FLASH MEMORY INTERFACE .............................................................................................................. 24
12.0 OTP Block Region .................................................................................................................................................... 24
12.1 OTP Block Protection ............................................................................................................................................ 24
13.0 ENHANCED BLOCK PROTECTION / UNPROTECTION ........................................................................................ 25
13.1 Block Protection..................................................................................................................................................... 26
13.1.1 Lock Register .................................................................................................................................................. 26
13.2 Persistent Protection Bits ...................................................................................................................................... 26
13.3 Dynamic Protection Bits ........................................................................................................................................ 27
13.4 Persistent Protection Bit Lock Bit .......................................................................................................................... 27
13.5 Password Protection Method................................................................................................................................. 27
13.6 Master locking bit set ............................................................................................................................................. 28
14.0 DEVICE STATUS FLAGS......................................................................................................................................... 36
15.0 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... 39
16.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )......................................................... 39
17.0 DC CHARACTERISTICS .......................................................................................................................................... 40
17.1 CAPACITANCE (TA = 25 °C, VCC = 3.0V, f = 1.0MHz) ....................................................................................... 40
18.0 AC TEST CONDITION.............................................................................................................................................. 41
19.0 AC CHARACTERISTICS .......................................................................................................................................... 41
19.1 Read Operations ................................................................................................................................................... 41
19.2 Write(Erase/Program)Operations .......................................................................................................................... 44
20.0 ERASE AND PROGRAM PERFORMANCE............................................................................................................. 45
21.0 PACKAGE DIMENSIONS......................................................................................................................................... 58
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K8P5516UZB-P(E)/I(C)(E)/4E
datasheet
Rev. 1.3
NOR FLASH MEMORY
256M Bit (16M x16, 32Mb x8) Page Mode / Page NOR Flash Memory
1.0 FEATURES
•
Single Voltage, 2.7V to 3.6V for Read and Write operations
•
Organization
16M x16 bit (Word mode)
32M x 8 bit (Byte mode)
•
Fast Read Access Time : 80ns
•
Page Mode Operation
8 Words Page access allows fast asychronous read
Page Read Access Time : 30ns
•
Uniform block architectures
64Kword x 256 (Uniform)
•
OTP Block : Extra 256 word
- 128word for factory and 128word for customer OTP
•
Power Consumption (typical value)
- Active Read Current : 30mA (@5MHz)
- Program/Erase Current : 25mA
- Standby Mode/Auto Sleep Mode : 20uA
•
Support Single & 32word Buffer Program
•
WP/ACC input pin
- Allows special protection of first or last block of flash array at V
IL
,
regardless of block protect status
- Removes special protection at V
IH,
the first or last block of flash array
return to normal block protect status
- Reduce program time at V
HH
: 6us/word at Write Buffer
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Mode
•
Hardware RESET Pin
•
Command Register Operation
•
Supports Common Flash Memory Interface
•
Industrial Temperature : -40°C to 85°C
•
Extended Temperature : -25°C to 85°C
•
Endurance : 100Kcycle
•
Vio options at 1.8V and 3V I/O
•
Package options
- 56 Pin TSOP (20x14mm)
- 64 Ball FBGA (11x13, 1.0mm Ball Pitch)
2.0 GENERAL DESCRIPTION
The K8P5516UZB featuring single 3.0V power supply, is an 256Mbit NOR-
type Flash Memory organized as 32M x 8 or 16M x16. The memory archi-
tecture of the device is designed to divide its memory arrays into 256 blocks
with independent hardware protection. This block architecture provides
highly flexible erase and program capability. The K8P5516UZB NOR Flash
consists of uniform block.
The K8P5516UZB offers page access time of 30ns with random access
time of 80ns. The device′s fast access times allow high speed microproces-
sors to operate without wait states. The device performs a program opera-
tion in unit of 16 bits (Word) and erases in units of a block. Single or multiple
blocks can be erased. The block erase operation is completed within typi-
cally 0.7 sec. The device requires 25mA as program/erase current in the
commercial and extended temperature ranges.
The K8P5516UZB NOR Flash Memory is created by using Samsung's
advanced CMOS process technology. This device is available in 64FBGA
and 56 Pin TSOP. The device is compatible with EPROM applications to
require high-density and cost-effective nonvolatile read/write storage solu-
tions.
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