Rev. 1.1, Sep. 2010
K8S1215ETC
K8S1215EBC
K8S1215EZC
512Mb C-die NOR FLASH
9x11, 64FBGA, 32M x16, Muxed Burst, Multi Bank SLC
1.7V ~ 1.95V
datasheet
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-1-
K8S1215E(T/B/Z)C
datasheet
History
Rev. 1.1
NOR FLASH MEMORY
Revision History
Revision No.
0.0
1.0
1.1
Draft Date
Mar. 31, 2010
May. 03, 2010
Sep. 06, 2010
Remark
Target
Final
Final
Editor
-
-
-
- First version for target specification.
- Specification is finalized.
- Added "CLK "HIGH" should be prohibited in asynchronous read
mode start (From CE LOW)" in Asynchronous read operation.
-2-
K8S1215E(T/B/Z)C
512Mb C-die NOR FLASH 1
datasheet
Rev. 1.1
NOR FLASH MEMORY
1.0 FEATURES................................................................................................................................................................. 5
2.0 GENERAL DESCRIPTION ......................................................................................................................................... 5
3.0 PIN DESCRIPTION .................................................................................................................................................... 5
4.0 64Ball FBGA TOP VIEW (BALL DOWN) .................................................................................................................... 6
5.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 7
6.0 ORDERING INFORMATION ...................................................................................................................................... 8
7.0 PRODUCT INTRODUCTION...................................................................................................................................... 11
8.0 COMMAND DEFINITIONS ......................................................................................................................................... 12
9.0 DEVICE OPERATION ................................................................................................................................................ 14
9.1 Read Mode .............................................................................................................................................................. 14
9.1.1 Asynchronous Read Mode................................................................................................................................ 14
9.1.2 Synchronous (Burst) Read Mode...................................................................................................................... 14
9.1.2.1 Continuous Linear Burst Read.................................................................................................................... 14
9.2 Programmable Wait State ....................................................................................................................................... 15
9.3 Handshaking............................................................................................................................................................ 15
9.4 Set Burst Mode Configuration Register ................................................................................................................... 15
9.4.1 Programmable Wait State Configuration........................................................................................................... 15
9.4.2 Burst Read Mode Setting .................................................................................................................................. 15
9.4.3 RDY Configuration ............................................................................................................................................ 16
9.5 Output Driver Setting ............................................................................................................................................... 17
9.6 Autoselect Mode...................................................................................................................................................... 17
9.7 Standby Mode ......................................................................................................................................................... 17
9.8 Automatic Sleep Mode ............................................................................................................................................ 17
9.9 Output Disable Mode ............................................................................................................................................... 17
9.10 Block Protection & Unprotection ............................................................................................................................ 18
9.11 Hardware Reset..................................................................................................................................................... 18
9.12 Software Reset ...................................................................................................................................................... 18
9.13 Program ................................................................................................................................................................. 18
9.14 Accelerated Program ............................................................................................................................................. 18
9.15 Write Buffer Programming ..................................................................................................................................... 19
9.16 Accelerated Write Buffer Programming ................................................................................................................. 19
9.17 Chip Erase ............................................................................................................................................................. 19
9.18 Block Erase ........................................................................................................................................................... 20
9.19 Blank check ........................................................................................................................................................... 20
9.20 Unlock Bypass....................................................................................................................................................... 20
9.21 Erase Suspend / Resume...................................................................................................................................... 20
9.22 Program Suspend / Resume ................................................................................................................................. 21
9.23 Read While Write Operation .................................................................................................................................. 21
9.24 OTP Block Region ................................................................................................................................................. 21
9.25 Low VCC Write Inhibit ........................................................................................................................................... 21
9.26 Write Pulse “Glitch” Protection .............................................................................................................................. 21
9.27 Logical Inhibit......................................................................................................................................................... 21
10.0 FLASH MEMORY STATUS FLAGS ......................................................................................................................... 22
11.0 Deep Power Down .................................................................................................................................................... 24
12.0 Common Flash Memory Interface............................................................................................................................. 25
13.0 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... 27
14.0 RECOMMENDED OPERATING CONDITIONS ....................................................................................................... 28
15.0 DC CHARACTERISTICS .......................................................................................................................................... 28
16.0 VCC POWER-UP...................................................................................................................................................... 29
17.0 CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)............................................................................................ 29
18.0 AC TEST CONDITION.............................................................................................................................................. 30
19.0 AC CHARACTERISTICS .......................................................................................................................................... 30
19.1 Synchronous/Burst Read....................................................................................................................................... 30
19.2 Asynchronous Read .............................................................................................................................................. 34
-3-
K8S1215E(T/B/Z)C
datasheet
Rev. 1.1
NOR FLASH MEMORY
19.3 Hardware Reset(RESET) ...................................................................................................................................... 36
19.4 Erase/Program Operation...................................................................................................................................... 37
19.5 Erase/Program Performance ................................................................................................................................. 38
20.0 Crossing of First Word Boundary in Burst Read Mode ............................................................................................. 45
-4-
K8S1215E(T/B/Z)C
datasheet
Rev. 1.1
NOR FLASH MEMORY
512M Bit (32M x16) Muxed Burst / Multi Bank SLC NOR Flash Memory
1.0 FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 33,554,432 x 16 bit (Word Mode Only)
•
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (32Mb Partition)
•
OTP Block : Extra 512-Word block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time : 100ns
- Synchronous Random Access Time : 95ns
- Burst Access Time :
11ns (66MHz) / 9ns (83MHz) / 7ns (108MHz) /6ns (133MHz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with Wrap
•
Block Architecture
- Uniform block part (K8S(10/11/12/13)15EZC) :
Five hundred twelve 64Kword blocks
- Boot block part (K8S(10/11/12/13)15ET(B)C) :
Four 16Kword blocks and five hundred eleven 64Kword blocks (Bank 0
contains four 16 Kword blocks and thirty-one 64Kword blocks, Bank 1 ~
Bank 15 contain four hundred eighty 64Kword blocks)
•
Reduce program time using the V
PP
•
Support 512-word Buffer Program
•
Power Consumption (Typical value, C
L
=30pF)
- Synchronous Read Current : 35mA at 133MHz
- Program/Erase Current : 25mA
- Read While Program/Erase Current : 45mA
- Standby Mode/Auto Sleep Mode : 30uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
(Boot block part : K8S(10/11/12/13)15ET(B)C)
- Last one block (BA511) is protected by WP=V
IL
(Uniform block part : K8S(10/11/12/13)15EZC)
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Blank Check Feature
•
Hardware Reset (RESET)
•
Deep Power Down Mode
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
- 100K Program/Erase cycles
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Output Driver Control by Configuration Register
•
Package : 64Ball FBGA type (9mm x 11mm), 0.5mm ball pitch
1.0mm(Max.)Thickness
2.0 GENERAL DESCRIPTION
The K8S(10/11/12/13)15E featuring single 1.8V power supply is a 512Mbit
Muxed Burst Multi Bank Flash Memory organized as 32Mx16. The memory
architecture of the device is designed to divide its memory arrays into
512blocks(Uniform block part)/515 blocks (Boot block part) with indepen-
dent hardware protection. This block architecture provides highly flexible
erase and program capability. The K8S(10/11/12/13)15E NOR Flash con-
sists of sixteen banks. This device is capable of reading data from one bank
while programming or erasing in the other bank. Regarding read access
time, the K8S10/1215E provides an 11ns burst access time and an 95ns
initial access time at 66MHz. At 83MHz, the K8S10/1215E provides an 9ns
burst access time and an 95ns initial access time. At 108MHz, the K8S11/
1315E provides an 7ns burst access time and an 95ns initial access time.
At 133MHz, the K8S11/1315E provides an 6ns burst access time and an
95ns initial access time. The device performs a program operation in units
of 16 bits (Word) and erases in units of a block. Single or multiple blocks
can be erased. The block erase operation is completed within typically
0.6sec. The device requires 25mA as program/erase current in the
extended temperature ranges.
The K8S(10/11/12/13)15E NOR Flash Memory is created by using Sam-
sung's advanced CMOS process technology.
3.0 PIN DESCRIPTION
Pin Name
A16 - A24
A/DQ0 - A/DQ15
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
DPD
Vcc
V
SS
Address Inputs
Multiplexed Address/Data input/output
Chip Enable
Output Enable
Hardware Reset
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Deep Power Down
Power Supply
Ground
Pin Function
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嵌入式系统
