K8S2815ET(B)C
NOR FLASH MEMORY
128Mb C-die SLC NOR Specification
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
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* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.2
November 2008
K8S2815ET(B)C
Document Title
NOR FLASH MEMORY
128M Bit (8M x16) Muxed Burst , Multi Bank NOR Flash Memory
Revision History
Revision No.
0.0
1.0
1.1
Initial issue
Specification is finalized.
History
Draft Date
Oct. 19, 2006
Jan. 21, 2008
Apr. 17, 2008
Remark
Target
Final
Extended Configuration Register option is added.
Enhanced Block Protection is added.
tCES @ 108MHz in AC Parameter table is changed from Min. 4.0ns to Min. 4.5ns.
1.2
Nov. 14, 2008
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
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Revision 1.2
November 2008
K8S2815ET(B)C
NOR FLASH MEMORY
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to
change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any ques-
tions, please contact the SAMSUNG branch office near you.
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Revision 1.2
November 2008
K8S2815ET(B)C
128Mb C-die SLC NOR Specification 1
NOR FLASH MEMORY
1. 0 FEATURES ................................................................................................................................................................2
1.1. GENERAL DESCRIPTION ..................................................................................................................................... 2
1.2. PIN DESCRIPTION................................................................................................................................................. 3
1.3. 44Ball FBGA TOP VIEW (BALL DOWN) ................................................................................................................ 4
1.4. FUNCTIONAL BLOCK DIAGRAM .......................................................................................................................... 5
2. 0 Ordering Information ..................................................................................................................................................6
3. 0 PRODUCT INTRODUCTION.....................................................................................................................................8
4. 0 COMMAND DEFINITIONS ........................................................................................................................................9
4.1. COMMAND DEFINITIONS ..................................................................................................................................... 9
5. 0 DEVICE OPERATION................................................................................................................................................11
5.1. Read Mode.............................................................................................................................................................. 11
5.2. Asynchronous Read Mode...................................................................................................................................... 11
5.3. Synchronous (Burst) Read Mode............................................................................................................................ 11
5.4. Output Driver Setting............................................................................................................................................... 12
5.5. Programmable Wait State ....................................................................................................................................... 12
5.6. Set Burst Mode Configuration Register................................................................................................................... 12
5.6.1
Extended Configuration Register (option : K8S2615ET(B)C, K8S2915ET(B)C only) ........................................ 13
5.7. Programmable Wait State Configuration................................................................................................................. 13
5.8. Burst Read Mode Setting ........................................................................................................................................ 13
5.9. RDY Configuration .................................................................................................................................................. 13
5.10. Autoselect Mode ................................................................................................................................................... 13
5.11. Standby Mode ....................................................................................................................................................... 14
5.12. Automatic Sleep Mode .......................................................................................................................................... 14
5.13. Output Disable Mode ............................................................................................................................................ 14
5.14. Block Protection & Unprotection ........................................................................................................................... 14
5.14.1 Enhanced Block Protection (option : K8S2715ET(B)C, K8S2915ET(B)C only) ................................................. 14
5.15. Hardware Reset .................................................................................................................................................... 19
5.16. Software Reset...................................................................................................................................................... 19
5.17. Program ................................................................................................................................................................ 19
5.18. Accelerated Program Operation............................................................................................................................ 19
5.19. Unlock Bypass ...................................................................................................................................................... 20
5.20. Chip Erase ............................................................................................................................................................ 20
5.21. Block Erase ........................................................................................................................................................... 20
5.22. Erase Suspend / Resume ..................................................................................................................................... 20
5.23. Program Suspend / Resume................................................................................................................................. 21
5.24. Read While Write Operation ................................................................................................................................. 21
5.25. OTP Block Region................................................................................................................................................. 21
5.26. Write Pulse “Glitch” Protection .............................................................................................................................. 21
5.27. Low VCC Write Inhibit ........................................................................................................................................... 22
5.28. Logical Inhibit ........................................................................................................................................................ 22
5.29. Power-up Protection.............................................................................................................................................. 22
5.30. FLASH MEMORY STATUS FLAGS ..................................................................................................................... 22
6. 0 Commom Flash Memory Interface.............................................................................................................................24
7. 0 ABSOLUTE MAXIMUM RATINGS.......................................................................................................................26
8. 0 DC CHARACTERISTICS
....................................................................................................................................26
9. 0 CAPACITANCE..........................................................................................................................................................28
10. 0 AC TEST CONDITION
......................................................................................................................................28
10.1. Asynchronous Read
....................................................................................................................................... 31
10.2. Hardware Reset(RESET)
............................................................................................................................... 34
10.3. Erase/Program Operation...............................................................................................................................
35
11. 0 FLASH Erase/Program Performance
................................................................................................................35
1
Revision 1.2
November 2008
K8S2815ET(B)C
NOR FLASH MEMORY
128M Bit (8M x16) Muxed Burst , Multi Bank NOR Flash Memory
1.0 FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 8,386,108 x 16 bit ( Word Mode Only)
•
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (8Mb Partition)
•
OTP Block : Extra 256-word block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time : 70ns
- Synchronous Random Access Time : 70ns
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz) / 9ns (83Mhz) / 7ns (108Mhz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with Wrap
•
Block Architecture
- Eight 4Kword blocks and two hundreds fifty-five 32Kword blocks
- Bank 0 contains eight 4 Kword blocks and fifteen 32Kword blocks
- Bank 1 ~ Bank 15 contain two hundred forty 32Kword blocks
•
Reduce program time using the V
PP
•
Support Single & Quad word accelerate program
•
Power Consumption (Typical value, C
L
=30pF)
- Burst Access Current : 24mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode : 15uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring
RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
- 100K Program / Erase cycles
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Package : Package : 44-ball FBGA Type, 7.7 x 6.2mm
0.5 mm ball pitch
1.0 mm (Max.) Thickness
1.1 GENERAL DESCRIPTION
The K8S2815E featuring single 1.8V power supply is a 128Mbit Syn-
chronous Burst Multi Bank Flash Memory organized as 8Mx16. The
memory architecture of the device is designed to divide its memory
arrays into 263 blocks with independent hardware protection. This
block architecture provides highly flexible erase and program capabil-
ity. The K8S2815E NOR Flash consists of sixteen banks. This device
is capable of reading data from one bank while programming or eras-
ing in the other bank.
Regarding read access time, the K8S2815E provides an 14.5ns
burst access time and an 70ns initial access time at 54MHz. At
66MHz, the K8S2815E provides an 11ns burst access time and 70ns
initial access time. At 83MHz, the K8S2815E provides an 9ns burst
access time and 70ns initial access time. At 108MHz, the K8S2815E
provides an 7ns burst access time and 70ns initial access time. The
device performs a program operation in units of 16 bits (Word) and an
erase operation in units of a block. Single or multiple blocks can be
erased. The block erase operation is completed within typically
0.7sec. The device requires 15mA as program/erase current in the
extended temperature ranges.
The K8S2815E NOR Flash Memory is created by using Samsung's
advanced CMOS process technology.
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.2
November 2008
