Rev. 1.0, Nov. 2010
K8S5615ETC
256Mb C-die NOR Flash
44FBGA, Muxed Burst, Multi Bank SLC
16M x16, 1.7V ~ 1.95V
datasheet
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-1-
K8S5615ETC
datasheet
NOR FLASH MEMORY
History
- First version for target specification.
- Preliminary datasheet.
- Added NOTE "Not 100% tested." for parameter "32-word Buffer Programming
Time" in 18.5 Erase/Program Performance table.
- Specification is finalized.
Draft Date
7, May, 2010
14, Oct. 2010
2, Nov. 2010
18, Nov. 2010
Remark
Target
Preliminary
Preliminary
Final
-
-
-
-
Rev. 1.0
Revision History
Revision No.
0.0
0.5
0.6
1.0
Editor
-2-
K8S5615ETC
256Mb C-die NOR Flash 1
datasheet
NOR FLASH MEMORY
Rev. 1.0
1.0 FEATURES................................................................................................................................................................. 5
2.0 GENERAL DESCRIPTION ......................................................................................................................................... 5
3.0 PIN DESCRIPTION .................................................................................................................................................... 5
4.0 44Ball FBGA TOP VIEW (BALL DOWN) .................................................................................................................... 6
5.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 7
6.0 ORDERING INFORMATION ...................................................................................................................................... 8
7.0 PRODUCT INTRODUCTION...................................................................................................................................... 11
8.0 COMMAND DEFINITIONS ......................................................................................................................................... 12
9.0 DEVICE OPERATION ................................................................................................................................................ 14
9.1 Read Mode .............................................................................................................................................................. 14
9.1.1 Asynchronous Read Mode................................................................................................................................ 14
9.1.2 Synchronous (Burst) Read Mode...................................................................................................................... 14
9.1.3 Continuous Linear Burst Read .......................................................................................................................... 14
9.2 Programmable Wait State ....................................................................................................................................... 15
9.3 Handshaking............................................................................................................................................................ 15
9.4 Set Burst Mode Configuration Register ................................................................................................................... 15
9.4.1 Programmable Wait State Configuration........................................................................................................... 15
9.4.2 Burst Read Mode Setting .................................................................................................................................. 15
9.4.3 RDY Configuration ............................................................................................................................................ 15
9.5 Autoselect Mode...................................................................................................................................................... 17
9.6 Standby Mode ......................................................................................................................................................... 17
9.7 Automatic Sleep Mode ............................................................................................................................................ 17
9.8 Output Disable Mode ............................................................................................................................................... 17
9.9 Block Protection & Unprotection.............................................................................................................................. 17
9.10 Hardware Reset..................................................................................................................................................... 17
9.11 Software Reset ...................................................................................................................................................... 18
9.12 Program ................................................................................................................................................................. 18
9.13 Accelerated Program ............................................................................................................................................. 18
9.14 Write Buffer Programming ..................................................................................................................................... 18
9.15 Accelerated Write Buffer Programming ................................................................................................................. 19
9.16 Chip Erase ............................................................................................................................................................. 19
9.17 Block Erase ........................................................................................................................................................... 19
9.18 Unlock Bypass....................................................................................................................................................... 19
9.19 Erase Suspend / Resume...................................................................................................................................... 20
9.20 Program Suspend / Resume ................................................................................................................................. 20
9.21 Read While Write Operation .................................................................................................................................. 20
9.22 OTP Block Region ................................................................................................................................................. 20
9.23 Low VCC Write Inhibit ........................................................................................................................................... 20
9.24 Write Pulse “Glitch” Protection .............................................................................................................................. 21
9.25 Logical Inhibit......................................................................................................................................................... 21
10.0 FLASH MEMORY STATUS FLAGS ......................................................................................................................... 22
11.0 Deep Power Down .................................................................................................................................................... 24
12.0 Common Flash Memory Interface............................................................................................................................. 25
13.0 ABSOLUTE MAXIMUM RATINGS
..................................................................................................................... 27
14.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )......................................................... 27
15.0 DC CHARACTERISTICS...................................................................................................................................
28
16.0 CAPACITANCE (TA = 25 °C, VCC = 1.8V, f = 1.0MHz)........................................................................................... 30
17.0 AC TEST CONDITION
...................................................................................................................................... 30
18.0 AC CHARACTERISTICS .......................................................................................................................................... 30
18.1 Synchronous/Burst Read.................................................................................................................................30
18.2 Asynchronous Read
........................................................................................................................................34
18.3 Hardware Reset(RESET) ...................................................................................................................................... 36
18.4 Erase/Program Operation...................................................................................................................................... 37
18.5 Erase/Program Performance
...........................................................................................................................38
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K8S5615ETC
datasheet
NOR FLASH MEMORY
Rev. 1.0
19.0 CROSSING OF FIRST WORD BOUNDARY IN BURST READ MODE ................................................................... 45
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K8S5615ETC
datasheet
NOR FLASH MEMORY
2.0 GENERAL DESCRIPTION
Rev. 1.0
256M Bit (16M x16) Muxed Burst / Multi Bank SLC NOR Flash Memory
1.0 FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 16,777,216 x 16 bit ( Word Mode Only)
•
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (16Mb Partition)
•
OTP Block : Extra 512-Word block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time : 100ns
- Synchronous Random Access Time :95ns
- Burst Access Time :
11ns (66MHz) / 9ns (83MHz) / 7ns (108MHz) /6ns (133MHz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with Wrap
•
Block Architecture
- Uniform block part (K8S(54/55/56/57)15EZC) : Two hundred fifty six
64Kword blocks
- Boot block part (K8S(54/55/56/57)15ET(B)C) : Four 16Kword blocks
and two hundred fifty five 64Kword blocks (Bank 0 contains four 16 Kword
blocks and fifteen 64Kword blocks, Bank 1 ~ Bank 15 contain two hundred
forty 64Kword blocks)
•
Reduce program time using the V
PP
•
Support 32-word Buffer Program
•
Power Consumption (Typical value, C
L
=30pF)
- Synchronous Read Current : 35mA at 133MHz
- Program/Erase Current : 25mA
- Read While Program/Erase Current : 45mA
- Standby Mode/Auto Sleep Mode : 30uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
(Boot block part : K8S(54/55/56/57)15ET(B)C)
- Last one block (BA255) is protected by WP=V
IL
(Uniform block part : K8S(54/55/56/57)15EZC)
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Deep Power Down Mode
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
- 100K Program/Erase cycles
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Output Driver Control by Configuration Register
•
Package : 44-Ball FBGA type (7.7mm x 6.2mm), 0.5mm ball pitch
1.0mm(Max.)Thickness
The K8S(54/55/56/57)15E featuring single 1.8V power supply is a 256Mbit
Muxed Burst Multi Bank Flash Memory organized as 16Mx16. The memory
architecture of the device is designed to divide its memory arrays into
256blocks(Uniform block part)/259 blocks(Boot block part) with indepen-
dent hardware protection. This block architecture provides highly flexible
erase and program capability. The K8S(54/55/56/57)15E NOR Flash con-
sists of sixteen banks. This device is capable of reading data from one bank
while programming or erasing in the other bank. Regarding read access
time, the K8S54/5615E provides an 11ns burst access time and an 95ns
initial access time at 66MHz. At 83MHz, the K8S54/5615E provides an 9ns
burst access time and an 95ns initial access time. At 108MHz, the K8S55/
5715E provides an 7ns burst access time and an 95ns initial access time.
At 133MHz, the K8S55/5715E provides an 6ns burst access time and an
95ns initial access time. The device performs a program operation in units
of 16 bits (Word) and erases in units of a block. Single or multiple blocks
can be erased. The block erase operation is completed within typically
0.6sec. The device requires 25mA as program/erase current in the
extended temperature ranges.
The K8S(54/55/56/57)15E NOR Flash Memory is created by using Sam-
sung's advanced CMOS process technology.
3.0 PIN DESCRIPTION
Pin Name
A16 - A23
A/DQ0 - A/DQ15
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
DPD
Vcc
V
SS
Pin Function
Address Inputs
Multiplexed Address/Data input/output
Chip Enable
Output Enable
Hardware Reset
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Deep Power Down
Power Supply
Ground
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