Rev. 1.2, Sep. 2010
K8S6815ET(B)D
64Mb D-die SLC NOR FLASH
7.5x5, 44FBGA, 8M Partition, x16, Muxed Burst, 8Banks
1.7V ~ 1.95V
datasheet
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K8S6815ET(B)D
datasheet
History
Rev. 1.2
NOR FLASH MEMORY
Revision History
Revision No.
0.0
1.0
1.1
1.2
- Initial issue
- Final datasheet.
- Added "CLK "HIGH" should be prohibited in asynchronous read
mode start (From CE LOW)" in Asynchronous read operation.
- Change t
RH
value ("Max 200ns" to "Min 200ns") in Vcc Power-up.
Draft Date
Jan.14, 2009
Mar. 30, 2010
Sep. 06, 2010
Sep. 15, 2010
Remark
Target
Final
Final
Final
Editor
-
-
-
-
-2-
K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
Table Of Contents
64Mb D-die SLC NOR FLASH
1.0 FEATURES................................................................................................................................................................. 4
2.0 GENERAL DESCRIPTION ......................................................................................................................................... 4
3.0 PIN DESCRIPTION .................................................................................................................................................... 5
4.0 PIN CONFIGURATION ............................................................................................................................................... 5
5.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 6
6.0 ORDERING INFORMATION ...................................................................................................................................... 6
7.0 PRODUCT INTRODUCTION...................................................................................................................................... 8
8.0 COMMAND DEFINITIONS ......................................................................................................................................... 9
9.0 DEVICE OPERATION ................................................................................................................................................ 11
9.1 Read Mode .............................................................................................................................................................. 11
9.1.1 Asynchronous Read Mode................................................................................................................................ 11
9.1.2 Synchronous (Burst) Read Mode...................................................................................................................... 11
9.2 Programmable Wait State ....................................................................................................................................... 12
9.3 Handshaking............................................................................................................................................................ 12
9.4 Set Burst Mode Configuration Register ................................................................................................................... 13
9.4.1 Extended Configuration Register (option : K8S6615ET(B)D only).................................................................... 13
9.4.2 Programmable Wait State Configuration........................................................................................................... 13
9.4.3 Burst Read Mode Setting .................................................................................................................................. 13
9.4.4 RDY Configuration ............................................................................................................................................ 13
9.5 Autoselect Mode...................................................................................................................................................... 14
9.6 Standby Mode ......................................................................................................................................................... 14
9.7 Automatic Sleep Mode ............................................................................................................................................ 14
9.8 Output Disable Mode ............................................................................................................................................... 14
9.9 Block Protection & Unprotection.............................................................................................................................. 14
9.10 Hardware Reset..................................................................................................................................................... 15
9.11 Software Reset ...................................................................................................................................................... 15
9.12 Program ................................................................................................................................................................. 15
9.13 Accelerated Program Operation ............................................................................................................................ 15
9.14 Unlock Bypass....................................................................................................................................................... 16
9.15 Chip Erase ............................................................................................................................................................. 16
9.16 Block Erase ........................................................................................................................................................... 16
9.17 Erase Suspend / Resume...................................................................................................................................... 16
9.18 Program Suspend / Resume ................................................................................................................................. 17
9.19 Read While Write Operation .................................................................................................................................. 17
9.20 OTP Block Region ................................................................................................................................................. 17
9.21 Low VCC Write Inhibit ........................................................................................................................................... 17
9.22 Logical Inhibit......................................................................................................................................................... 17
9.23 Power-up Protection .............................................................................................................................................. 17
10.0 FLASH MEMORY STATUS FLAGS ......................................................................................................................... 18
11.0 COMMON FLASH MEMORY INTERFACE .............................................................................................................. 20
12.0 ABSOLUTE MAXI010MUM RATINGS ..................................................................................................................... 22
13.0 RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND)........................................................... 22
14.0 DC CHARACTERISTICS .......................................................................................................................................... 22
15.0 CAPACITANCE (TA = 25 °C, VCC = 1.8V, f = 1.0MHz)........................................................................................... 24
16.0 AC TEST CONDITION.............................................................................................................................................. 24
17.0 AC CHARACTERISTICS .......................................................................................................................................... 25
17.1 Synchronous/Burst Read....................................................................................................................................... 25
17.2 Asynchronous Read .............................................................................................................................................. 29
17.3 Hardware Reset(RESET) ...................................................................................................................................... 31
17.4 Erase/Program Operation...................................................................................................................................... 32
17.5 FLASH Erase/Program Performance .................................................................................................................... 32
18.0 CROSSING OF FIRST WORD BOUNDARY IN BURST READ MODE ................................................................... 39
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K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
4M Bit (
8M Partition, x16) Muxed Burst, 8 Banks, NOR Flash Memory
1.0 FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 4,194,304 x 16 bit (Word Mode Only)
•
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 8 Banks (8Mb Partition)
•
OTP Block : Extra 256word block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time : 70ns
- Synchronous Random Access Time : 70ns
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz) / 9ns (83Mhz) / 7ns (108Mhz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with Wrap
•
Block Architecture
- Eight 4Kword blocks and one hundred twenty seven 32Kword
blocks
- Bank 0 contains eight 4 Kword blocks and fifteen 32Kword
blocks
- Bank 1~Bank 7 contain one hundred twelve 32Kword blocks
•
Reduce program time using the V
PP
•
Support Single & Quad word accelerate program
•
Power Consumption (Typical value, C
L
=30pF)
- Burst Access Current : 24mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode : 15uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring
RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
100K Program/Erase Cycles Minimum
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Package : Package : 44-ball FBGA Type, 7.5 x 5 mm
0.5 mm ball pitch
1.0 mm (Max.) Thickness
2.0 GENERAL DESCRIPTION
The K8S6815E featuring single 1.8V power supply is a 64Mbit Synchro-
nous Burst 8Bank Flash Memory organized as 8M, x16. The memory archi-
tecture of the device is designed to divide its memory arrays into 135 blocks
with independent hardware protection. This block architecture provides
highly flexible erase and program capability. The K8S6815E NOR Flash
consists of eight banks. This device is capable of reading data from one
bank while programming or erasing in the other bank.
Regarding read access time, the K8S6815E provides an 14.5ns burst
access time and an 70ns initial access time at 54MHz. At 66MHz, the
K8S6815E provides an 11ns burst access time and 70ns initial access time.
At 83MHz, the K8S6815E provides an 9ns burst access time and 70ns ini-
tial access time. At 108MHz, the K8S6815E provides an 7ns burst access
time and 70ns initial access time. The device performs a program operation
in units of 16bits (Word) and an erase operation in units of a block. Single or
multiple blocks can be erased. The block erase operation is completed
within typically 0.7sec. The device requires 15mA as program/erase current
in the extended temperature ranges.
The K8S6815E NOR Flash Memory is created by using Samsung's
advanced CMOS process technology.
-4-
K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
3.0 PIN DESCRIPTION
Pin Name
A16 - A21
A/DQ0 - A/DQ15
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
Vcc
V
SS
Pin Function
Address Inputs
Multiplexed Address/Data input/output
Chip Enable
Output Enable
Hardware Reset Pin
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Power Supply
Ground
4.0 PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
A
RDY
A21
V
SS
CLK
V
CC
WE
V
PP
A19
A17
NC
B
V
CC
A16
A20
AVD
NC
RESET
WP
A18
CE
V
SS
C
V
SS
A/DQ7
A/DQ6
A/DQ13
A/DQ12
A/DQ3
A/DQ2
A/DQ9
A/DQ8
OE
D
A/DQ15
A/DQ14
V
SS
A/DQ5
A/DQ4
A/DQ11
A/DQ10
V
CC
A/DQ1
A/DQ0
44-FBGA : Top View (Ball Down)
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