K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
FLASH MEMORY
Document Title
128M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0
0.1
Initial issue.
1. Note 1 ( Program/Erase Characteristics) is added( page 13 )
2. NAND Flash Technical Notes is changed.
-Invalid block -> initial invalid block ( page 15 )
-Error in write or read operation ( page 16 )
-Program Flow Chart ( page 16 )
3. Vcc range is changed
-1.7V~1.95V ->1.65V~1.95V
4. 2.7V device is added
5
. Multi plane operation and Copy-Back Program are not supported with 1.8V
device.
Draft Date
Mar. 17th 2003
Oct. 11th 2004
Remark
Advance
Advance
0.2
1.0
1. The flow chart to creat the initial invalid block table is changed.
May 6th. 2005
Preliminary
May 30th 2005 Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
1
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
FLASH MEMORY
128M x 8 Bit Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9K1G08R0B-G,J
K9K1G08B0B-G,J
K9K1G08U0B-G,J
Vcc Range
1.65 ~ 1.95V
2.5 ~ 2.9V
2.7 ~ 3.6V
X8
FBGA
Organization
PKG Type
FEATURES
•
Voltage Supply
- 1.8V device(K9K1G08R0B) : 1.65 ~ 1.95V
- 2.7V device(K9K1G08B0B) : 2.5 ~ 2.9V
- 3.3V device(K9K1GXXU0B) : 2.7 ~ 3.6 V
•
Organization
- Memory Cell Array
-128M + 4096K)bit x 8 bit
- Data Register
- (512 + 16)bit x 8bit
•
Automatic Program and Erase
- Page Program
- (512 + 16)Byte
- Block Erase :
- (16K + 512)Byte
•
Page Read Operation
- Page Size
- (512 + 16)Byte
- Random Access
: 15µs(Max.)
- Serial Page Access : 50ns(Min.)*
* K9K1G08R0B : 60ns
•
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Intelligent Copy-Back
•
Unique ID for Copyright Protection
•
Package
- K9K1G08X0B-GCB0/GIB0
63- Ball FBGA
- K9K1G08X0B-JCB0/JIB0
63- Ball FBGA - Pb-free Package
GENERAL DESCRIPTION
The K9K1G08X0B is a 128M(134,217,728)x8bit NAND Flash Memory with a spare 4.096K(4,194,304)x8bit. Its NAND cell provides
the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typically 200µs on
the 528-byte page and an erase operation can be performed in typically 2ms on a 16K-byte block. Data in the data register can be
read out at 50ns(1.8V device : 60ns) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as
command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required,
and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9K1G08X0B′s extended reli-
ability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The
K9K1G08X0B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
2
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
PIN CONFIGURATION (FBGA)
K9K1G08X0B-GCB0,JCB0/GIB0,JIB0
FLASH MEMORY
1
N.C N.C
2
3
4
5
6
N.C N.C
N.C N.C
A
B
C
N.C
/WP
NC
NC
NC
NC
NC
NC
Vss
ALE
/RE
NC
NC
NC
I/O0
I/O1
I/O2
Vss
CLE
NC
NC
NC
NC
NC
/CE
NC
NC
NC
NC
NC
/WE
NC
NC
NC
NC
NC
R/B
NC
NC
NC
NC
Vcc
I/O7
Vss
D
E
F
G
H
VccQ I/O5
I/O6
I/O3 I/O4
N.C N.C
N.C N.C
N.C N.C
N.C N.C
Top View
3
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
FLASH MEMORY
Top View
Bottom View
#A1 INDEX MARK(OPTIONAL)
8.50
±0.10
6
8.50
±0.10
0.80 x 9= 7.20
0.80 x 5= 4.00
0.80
5 4 3 2
A
1
B
#A1
(Datum A)
A
B
0.80 x 11= 8.80
0.80 x 7= 5.60
2.00
0.45
±0.05
1.20
(Max)
0.25
(Min.)
(Datum B)
C
D
E
0.80
13.50
±0.10
2.80
F
G
H
63-∅0.45
±0.05
∅
0.20
M
A B
Side View
13.50
±0.10
0.10MAX
4
13.50
±0.10
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
PIN DESCRIPTION
Pin Name
I/O
0
~ I/O
7
(K9K1G08X0B)
Pin Function
FLASH MEMORY
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation .
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
OUTPUT BUFFER POWER
Vcc
Q
is the power supply for Output Buffer.
Vcc
Q
is internally connected to Vcc, thus should be biased to Vcc.
POWER
V
CC
is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
DO NOT USE
Leave it disconnected.
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Q
Vcc
Vss
N.C
DNU
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
5
stm32/stm8
