K9W8G08U1M
K9K4G08Q0M
K9K4G08U0M
K9K4G16Q0M
K9K4G16U0M
FLASH MEMORY
Document Title
512M x 8 Bit / 256M x 16 Bit
NAND Flash Memory
Revision History
Revision No
0.0
0.1
0.2
History
1. Initial issue
1. Add two-K9K4GXXU0M-YCB0/YIB0 Stacked Package
1. The 3rd Byte ID after 90h ID read command is don’ cared.
t
The 5th Byte ID after 90h ID read command is deleted.
1. The K9W8G16U1M-YCB0,YIB0,PCB0,PIB0 is deleted in line up.
2. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
3. Pb-free Package is added.
K9K4G08Q0M-PCB0,PIB0
K9K4G08U0M-PCB0,PIB0
K9K4G16U0M-PCB0,PIB0
K9K4G16Q0M-PCB0,PIB0
K9W8G08U1M-PCB0,PIB0
1. Added Addressing method for program operation.
1. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns
-
tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
2. Added addressing method for program operation
3. PKG(TSOP1) Dimension Change
Draft Date
Feb. 19. 2003
Mar. 31. 2003
Apr. 9. 2003
Remark
Advance
Preliminary
Preliminary
0.3
Apr. 30. 2003
Preliminary
0.4
0.5
Jan. 27. 2004
May.31. 2004
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9W8G08U1M
K9K4G08Q0M
K9K4G08U0M
K9K4G16Q0M
K9K4G16U0M
FLASH MEMORY
512M x 8 Bit / 256M x 16 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9K4G08Q0M-Y
K9K4G16Q0M-Y
K9XXG08UXM-Y
K9K4G16U0M-Y
2.7 ~ 3.6V
Vcc Range
1.70 ~ 1.95V
Organization
X8
X16
X8
X16
TSOP1
PKG Type
FEATURES
•
Voltage Supply
-1.8V device(K9K4GXXQ0M): 1.70V~1.95V
-3.3V device(K9XXGXXUXM): 2.7 V ~3.6 V
•
Organization
- Memory Cell Array
-X8 device(K9XXG08XXM) : (512M + 16,384K)bit x 8bit
-X16 device(K9XXG16XXM) : (256M + 8,192K)bit x 16bit
- Data Register
-X8 device(K9XXG08XXM): (2K + 64)bit x8bit
-X16 device(K9XXG16XXM): (1K + 32)bit x16bit
- Cache Register
-X8 device(K9XXG08XXM) : (2K + 64)bit x8bit
-X16 device(K9XXG16XXM) : (1K + 32)bit x16bit
•
Automatic Program and Erase
- Page Program
-X8 device(K9XXG08XXM) : (2K + 64)Byte
-X16 device(K9XXG16XXM) : (1K + 32)Word
- Block Erase
-X8 device(K9XXG08XXM) : (128K + 4K)Byte
-X16 device(K9XXG16XXM) : (64K + 2K)Word
•
Page Read Operation
- Page Size
- X8 device(K9XXG08XXM) : 2K-Byte
- X16 device(K9XXG16XXM) : 1K-Word
- Random Read : 25µs(Max.)
- Serial Access : 50ns(Min.)
30ns(Min., K9XXG08UXM only)
•
Fast Write Cycle Time
- Program time : 300µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Cache Program Operation for High Performance Program
•
Power-On Auto-Read Operation
•
Intelligent Copy-Back Operation
•
Unique ID for Copyright Protection
•
Package :
- K9XXGXXXXM-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9W8G08U1M-YCB0/YIB0 : Two K9K4G08U0M stacked.
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9XXGXXXXM-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9W8G08U1M-PCB0/PIB0 : Two K9K4G08U0M stacked.
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
GENERAL DESCRIPTION
Offered in 512Mx8bit or 256Mx16bit, the K9XXGXXXXM is 4G bit with spare 128M bit capacity. Its NAND cell provides the most
cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112-
byte(X8 device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device)
or 64K-word(X16 device) block. Data in the data page can be read out at 50ns cycle time per byte(30ns, only X8 3.3v device) or
word(X16 device). The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write
controller automates all program and erase functions including pulse repetition, where required, and internal verification and margin-
ing of data. Even the write-intensive systems can take advantage of the K9XXGXXXXM′s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9XXGXXXXM is an optimum solution for
large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. An ultra
high density solution having two 4Gb stacked with two chip selects is also available in standard TSOPI package.
2
K9W8G08U1M
K9K4G08Q0M
K9K4G08U0M
K9K4G16Q0M
K9K4G16U0M
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9K4GXXXXM-YCB0,PCB0/YIB0,PIB0
X16
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
X8
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
X8
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
PRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
X16
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
PRE
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
48-pin TSOP1
Standard Type
12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
0.10
MAX
0.004
#48
( 0.25 )
0.010
12.40
0.488 MAX
#24
#25
1.00
±0.05
0.039
±0.002
0.25
0.010 TYP
18.40
±0.10
0.724
±0.004
+0.075
20.00
±0.20
0.787
±0.008
0.20
-0.03
+0.07
#1
0.008
-0.001
0.16
-0.03
+0.07
+0.003
0.50
0.0197
12.00
0.472
0.05
0.002 MIN
0.125
0.035
0~8°
0.45~0.75
0.018~0.030
( 0.50 )
0.020
3
0.005
-0.001
+0.003
1.20
0.047MAX
K9W8G08U1M
K9K4G08Q0M
K9K4G08U0M
K9K4G16Q0M
K9K4G16U0M
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9W8G08U1M-YCB0,PCB0/YIB0,PIB0
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
PRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
48-pin TSOP1
Standard Type
12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
0.10
MAX
0.004
#48
( 0.25 )
0.010
12.40
0.488 MAX
#24
#25
1.00
±0.05
0.039
±0.002
0.25
0.010 TYP
18.40
±0.10
0.724
±0.004
+0.075
20.00
±0.20
0.787
±0.008
0.20
-0.03
+0.07
#1
0.008
-0.001
0.16
-0.03
+0.07
+0.003
0.50
0.0197
12.00
0.472
0.02
0.002 MIN
0.125
0.035
0~8°
0.45~0.75
0.018~0.030
( 0.50 )
0.020
4
0.005
-0.001
+0.003
1.20
0.047MAX
K9W8G08U1M
K9K4G08Q0M
K9K4G08U0M
K9K4G16Q0M
K9K4G16U0M
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O
0
~ I/O
7
(K9XXG08XXM)
I/O
0
~ I/O
15
(K9K4G16X0M)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is
ignored, and the device does not return to standby mode in program or erase operation. Regarding CE /
CE1 control during read operation, refer to ’
Page read’section of Device operation .
CHIP ENABLE
The CE2 input enables the second K9K4GXXU0M
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program,
erase or random read operation is in process and returns to high state upon completion. It is an open drain
output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to Vcc.
POWER
V
CC
is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
CLE
ALE
CE / CE1
CE2
RE
WE
WP
R/B1/ R/B2
PRE
Vcc
Vss
N.C
NOTE:
Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
5
