KAF-09000
3056 (H) x 3056 (V) Full
Frame CCD Image Sensor
Description
Combining high resolution with outstanding sensitivity, the
KAF−09000 image sensor has been specifically designed to meet the
needs of next−generation low cost digital radiography and scientific
imaging systems. The high sensitivity available from 12−micron
square pixels combines with a low noise architecture to allow system
designers to improve overall image quality, or to relax system
tolerances to achieve lower cost. The excellent uniformity of the
KAF−09000 image sensor improves overall image integrity by
simplifying image corrections, while integrated anti−blooming
protection prevents image bleed from over−exposure in bright areas of
the image. To simplify device integration, the KAF−09000 image
sensor uses the same pin−out and package as the KAF−16801 image
sensor.
The sensor utilizes the TRUESENSE Transparent Gate Electrode to
improve sensitivity compared to the use of a standard front−side
illuminated polysilicon electrode.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Typical Value
Full Frame CCD [Square Pixels]
3103 (H) x 3086 (V) = 9.6 Mp
3085 (H) x 3085 (V) = 9.5 Mp
3056 (H) x 3056 (V) = 9.3 Mp
12
mm
(H) x 12
mm
(V)
36.7 mm (H) x 36.7 mm (V)
51.9 mm diagonal,
645 1.3x optical format
Square
1
110 ke
−
24
mV/e
−
64%
2595 ke/mJ/cm
2
62.3 V/mJ/cm
2
7 e
−
5 e/pix/sec
7°C
84 dB
> 100 X saturation exposure
10 MHz
CERDIP, (sidebrazed pins, CuW)
AR coated 2 sides Taped Clear
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Figure 1. KAF−09000 CCD Image Sensor
Features
•
TRUESENSE Transparent Gate Electrode
•
•
•
•
•
for High Sensitivity
Large Pixel Size
Large Image Area
High Quantum Efficiency
Low Noise Architecture
Broad Dynamic Range
Aspect Ratio
Horizontal Outputs
Saturation Signal
Output Sensitivity
Quantum Efficiency (550 nm)
Responsivity (550 nm)
Read Noise (f = 3 MHz)
Dark Signal (T = 25°C)
Dark Current Doubling Temperature
Linear Dynamic Range (f = 4 MHz)
Blooming Protection
(4 ms exposure time)
Maximum Data Rate
Package
Cover Glass
Applications
•
Medical
•
Scientific
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
1
Publication Order Number:
KAF−09000/D
©
Semiconductor Components Industries, LLC, 2015
February, 2015
−
Rev. 3
KAF−09000
ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number
KAF−09000−ABA−DP−BA
KAF−09000−ABA−DP−AE
KAF−09000−ABA−DD−BA
KAF−09000−ABA−DD−AE
Description
Monochrome, Microlens, CERDIP Package, (sidebrazed, CuW),
Taped clear coverglass, Standard grade
Monochrome, Microlens, CERDIP Package, (sidebrazed, CuW),
Taped clear coverglass, Engineering sample
Monochrome, Microlens, CERDIP Package, (sidebrazed, CuW),
AR coated 2 sides, Standard grade
Monochrome, Microlens, CERDIP Package, (sidebrazed, CuW),
AR coated 2 sides, Engineering sample
Marking Code
KAF−09000−ABA
[Serial Number]
See the ON Semiconductor
Device Nomenclature
document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−09000
DEVICE DESCRIPTION
Architecture
1 Test Row
V1
V2
9
KAF−
09000
4 1 3 20
LOD
3056 H x 3056 V
12
μm
x 12
μm
Pixels
9 1 8
OG
RD
RG
VDD
VOUT
VSS
SUB
H1
H2
20 Dark
1 6 4 1 3 20
3056
9 1 2
Figure 2. Block Diagram
Dark Reference Pixels
The periphery of the device is surrounded with a border of
light shielded pixels creating a dark region. Within this dark
region, there are 20 leading dark pixels on every line as well
as 20 full dark lines at the start and 9 full dark lines at the end
of every frame. Under normal circumstances, these pixels do
not respond to light and may be used as a dark reference.
Dummy Pixels
formation of potential wells at each pixel site. The number
of electrons collected is linearly dependent on light level and
exposure time and non−linearly dependent on wavelength.
When the pixel’s capacity is reached, excess electrons are
discharged into the lateral overflow drain to prevent
crosstalk or ‘blooming’. During the integration period, the
V1 and V2 register clocks are held at a constant (low) level.
Charge Transport
Within each horizontal shift register there are 14 leading
pixels and 3 trailing pixels. These are designated as dummy
pixels and should not be used to determine a dark reference
level.
Image Acquisitio
n
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the device. These
photon−induced electrons are collected locally by the
The integrated charge from each pixel is transported to the
output using a two−step process. Each line (row) of charge
is first transported from the vertical CCDs to a horizontal
CCD register using the V1 and V2 register clocks. The
horizontal CCD is presented a new line on the falling edge
of V2 while H1 is held high. The horizontal CCDs then
transport each line, pixel by pixel, to the output structure by
alternately clocking the H1 and H2 pins in a complementary
fashion.
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KAF−09000
HORIZONTAL REGISTER
Output Structure
H2
H1
HCCD
Charge
Transfer
VDD
OG
RG
RD
Floating
Diffusion
VOUT
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 3. Output Architecture (Left or Right)
The output consists of a floating diffusion capacitance
connected to a three−stage source follower. Charge
presented to the floating diffusion (FD) is converted into a
voltage and is current amplified in order to drive off−chip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the FD.
Once the signal has been sampled by the system electronics,
the reset gate (RG) is clocked to remove the signal and FD
is reset to the potential applied by reset drain (RD).
Increased signal at the floating diffusion reduces the voltage
seen at the output pin. To activate the output structure, an
off−chip current source must be added to the VOUT pin of
the device. See Figure 4.
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4
KAF−09000
Output Load
VDD = +15 V
Iout = 5 mA
0.1
μF
VOUT
2N3904
or Equiv.
140
W
1 kW
Buffered
Video
Output
Note: Component values may be revised based on operating conditions and other design considerations.
Figure 4. Recommended Output Structure Load Diagram
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