KAF-16200
4500 (H) x 3600 (V) Full
Frame CCD Image Sensor
Description
The KAF−16200 is a single output, high performance CCD (charge
coupled device) image sensor with 4500 (H) x 3600 (V) photoactive
pixels designed for a wide range of color or monochrome image
sensing applications. Each pixel contains anti−blooming protection by
means of a lateral overflow drain thereby preventing image corruption
during high light level conditions. Each of the 6.0
mm
square pixels of
the color version are selectively covered with red, green or blue
pigmented filters for color separation. Microlenses are added for
improved sensitivity on both color and monochrome sensors.
The sensor utilizes a transparent gate electrode to improve
sensitivity compared to the use of a standard front side illuminated
polysilicon electrode.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Aspect Ratio
Output Sensitivity (Q/V)
Charge Capacity (24 MHz)
Read Noise (f = 24 MHz)
Dark Current (60°C)
Dynamic Range
Quantum Efficiency (Peak)
Color (600, 549, 480 nm)
Monochrome (540 nm)
Maximum Frame Rate
Maximum Data Rate
Blooming Protection
Typical Value
Full Frame CCD with Square Pixels
4641 (H) x 3695 (V) = 17.0 M
4540 (H) x 3640 (V) = 16.5 M
4500 (H) x 3600 (V) = 16.2 M
6.0
mm
(H) x 6.0
mm
(V)
27.0 mm (H) x 21.6 mm (V)
34.6 mm Diag., APS−H Optical Format
5:4
31
mV/e
−
41 ke
−
14 e
−
rms
112 e
−
/s
69 dB linear
33%, 40%, 33%
56%
1.23 fps
24 MHz
2000 X Saturation Exposure
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Figure 1. KAF−16200 CCD Image Sensor
Features
•
Transparent Gate Electrode for High
•
•
•
•
Sensitivity
High Resolution, 35 mm Diagonal Format
Broad Dynamic Range
Low Noise
Large Image Area
Applications
•
Astrophotography
•
Scientific Imaging
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: Unless noted, all parameters are specified at 25°C.
©
Semiconductor Components Industries, LLC, 2016
January, 2017
−
Rev. 2
1
Publication Order Number:
KAF−16200/D
KAF−16200
ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number
KAF−16200−ABA−CD−B1
KAF−16200−ABA−CD−B2
KAF−16200−ABA−CD−AE
KAF−16200−FXA−CD−B1
KAF−16200−FXA−CD−B2
KAF−16200−FXA−CD−AE
Description
Monochrome, Microlens, CERDIP Package, Sealed Clear Cover
Glass with AR Coating (both sides), Grade 1
Monochrome, Microlens, CERDIP Package, Sealed Clear Cover
Glass with AR Coating (both sides), Grade 2
Monochrome, Microlens, CERDIP Package, Sealed Clear Cover
Glass with AR Coating (both sides), Engineering Grade
Gen2 Color (Bayer RGB), Special Microlens, CERDIP Package,
Sealed Clear Cover Glass with AR Coating (both sides), Grade 1
Gen2 Color (Bayer RGB), Special Microlens, CERDIP Package,
Sealed Clear Cover Glass with AR Coating (both sides), Grade 2
Gen2 Color (Bayer RGB), Special Microlens, CERDIP Package,
Sealed Clear Cover Glass with AR Coating (both sides), Engineering
Grade
KAF−16200−FXA
Serial Number
Marking Code
KAF−16200−ABA
Serial Number
See the ON Semiconductor
Device Nomenclature
document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−16200
DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram
Dark Reference Pixels
Surrounding the periphery of the device is a border of light
shielded pixels creating a dark region. Within this dark
region are light shielded pixels that include 36 leading dark
pixels on every line. There are also 30 full dark lines at the
start and 23 full dark lines at the end of every frame. Under
normal circumstances, these pixels do not respond to light
and may be used as a dark reference.
Dummy Pixels
Image Acquisitio
n
Within each horizontal shift register there are 20 leading
additional shift phases 1 + 10 + 4 + 1 + 4 (See Figure 2).
These pixels are designated as dummy pixels and should not
be used to determine a dark reference level.
Active Buffer Pixels
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the device. These
photon−induced electrons are collected locally by the
formation of potential wells at each photogate or pixel site.
The number of electrons collected is linearly dependent on
light level and exposure time and non−linearly dependent on
wavelength. When the pixel’s capacity is reached, excess
electrons are discharged into the lateral overflow drain to
prevent crosstalk or ‘blooming’. During the integration
period, the V1 and V2 register clocks are held at a constant
(low) level.
Charge Transpor
t
Forming the outer boundary of the effective active pixel
region, there are 20 unshielded active buffer pixels between
the photoactive area and the dark reference. These pixels are
light sensitive but they are not tested for defects and
non−uniformities. For the leading 20 active column pixels,
the first 4 pixels are covered with blue pigment while the
remaining are arranged in a Bayer pattern (R, GR, GB, B).
CTE Monitor Pixels
Two CTE test columns, one on each of the leading and
trailing ends and one CTE test row are included for
manufacturing test purposes.
The integrated charge from each photogate (pixel) is
transported to the output using a two−step process. Each line
(row) of charge is first transported from the vertical CCDs
to a horizontal CCD register using the V1 and V2 register
clocks. The horizontal CCD is presented with a new line on
the falling edge of V2 while H1 is held high. The horizontal
CCDs then transport each line, pixel by pixel, to the output
structure by alternately clocking the H1 and H2 pins in a
complementary fashion. A separate connection to the last
H1 phase (H1L) is provided to improve the transfer speed of
charge to the floating diffusion output amplifier. On each
falling edge of H1L a new charge packet is dumped onto a
floating diffusion and sensed by the output amplifier.
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3
KAF−16200
HORIZONTAL REGISTER
Output Structure
H2
H1
HCCD
Charge
Transfer
VDD
H1L
OG
RG
RD
Floating
Diffusion
VOUTX
X= L or R
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Note: Represents either the left or the right output. The designation is omitted in the figure.
Figure 3. Output Architecture (Left or Right)
The output consists of a floating diffusion capacitance
connected to a three−stage source follower. Charge
presented to the floating diffusion (FD) is converted into a
voltage and is current amplified in order to drive off−chip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the FD.
Once the signal has been sampled by the system electronics,
the reset gate (RG) is clocked to remove the signal and FD
is reset to the potential applied by reset drain (RD).
Increased signal at the floating diffusion reduces the voltage
seen at the output pin. To activate the output structures, an
off−chip current source must be added to the VOUT pins of
the device. See Figure 4.
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4
KAF−16200
Output Load
VDD = +15 V
Iout = 5 mA
0.1
μF
VOUT
2N3904
or Equiv.
140
W
1 kW
Buffered
Video
Output
Note: Component values may be revised based on operating conditions and other design considerations.
Figure 4. Recommended Output Structure Load Diagram
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5
DSP 与 ARM 处理器
