MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
MuxOneNAND
TM
Specification
Density
1Gb
2Gb
Part No.
KFM1G16Q2M-DEB5
KFN2G16Q2M-DEB5
V
CC
(core & IO)
1.8V(1.7V~1.95V)
1.8V(1.7V~1.95V)
Temperature
Extended
Extended
PKG
63FBGA(LF)
63FBGA(LF)
Version: Ver. 1.2
Date: Dec. 23, 2005
1
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
1.0
INTRODUCTION
This specification contains information about the Samsung Electronics Company MuxOneNAND
™
‚ Flash memory product family.
Section 1.0 includes a general overview, revision history, and product ordering information.
Section 2.0 describes the MuxOneNAND device. Section 3.0 provides information about device operation. Electrical specifications
and timing waveforms are in Sections 4.0 though 6.0. Section 7.0 provides additional application and technical notes pertaining to
use of the MuxOneNAND. Package dimensions are found in Section 8.0
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
MuxOneNAND
™
‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of
their rightful owners.
Copyright
©
2005, Samsung Electronics Company, Ltd
2
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
1.1
Revision History
Document Title
MuxOneNAND
Revision History
Revision No. History
0.0
0.1
Initial issue.
1. Corrected the errata
2. Added Data Protection Scheme during Power-down
3. ECC description is revised.
4. Added Read while Load and Write While Program diagram.
5. Revised and added OTP description.
6. Added Write Protection description
7. Added Multi Block Erase operation notes
8. Added NAND Array Memory Map
9. RDY Conf bit in System Configuration Register is added.
10. Controller Status Register is revised.
11. Added DC/AC parameters
12. Revised OTP area assignment
13. Added the Addressing for program operation
14. Added INT guidance
15. Added Reset descriptions.
16. Revised Status Flag
1. Updated all description with a new format
Draft Date
Dec. 3, 2003
May 19, 2004
Remark
Draft
Advance
0.2
0.3
Nov. 4, 2004
Preliminary
Preliminary
1. Corrected the errata
Jan. 10, 2005
2. Revised typical value of ISB from 50uA to 10uA
3. Revised maximum value of ISB from 100uA to 50uA
4. Revised erase current as TBD
5. Revised maximum value of tCE, tAA and tACC from 70ns to 76ns
6. Revised Vcc-IO description
7. Revised Spare Area description
8. Added Version ID Register information
9. Added extra information on Controller Status Register
10. Added commands related to Interrupt Status Register bits
11. Revised Write Protection Status on Chapter 3.4.3
12. Revised Copy-Back Program Operation description
13. Added Copy-Back Program Operation with Random Data Input
14. Added extra information on Multi-Block Erase Operation
15. Disabled FBA restriction in OTP operation
16. Revised Cache Read Flow Chart
17. Added DQ6 Toggle Bit Information on Chapter 3.13
18. Added ISB information on DDP
19. Revised Reset Parameter descriptions
20. Added Asynchronous Write timing diagram
21. Added RDY information on Warm Reset Timing diagram
22. Added information on Data Protection Timing During Power Down
23. Added Toggle Bit Timing in Asynchronous Read timing diagram
24. Revised Interrupt pin rise and falling slope graph
25. Added restriction on address register setting on Dual Operations
26. Added restriction on address register setting on Cache Read Operation
27. Added Technical Note
3
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
Revision History
Revision No. History
0.4
1. Corrected the errata
2. Updated DC parameters to RMS Values
3. Revised Warm Reset Timing Diagram
4. Added INT Capacitance Information
5. Added Speed Information Ordering Information
6. Added Booting Sequence in Technical Note
7. Revised OTP Program and Lock Flow Chart
8. Revised tOEZ description on Chapter 5.5
9. Revised tASO value to 10ns
10. Added RDY and INT Pin behavior before IOBE=1
11. Added Erase suspend and Resume Information for Multi Block Erase
12. Added I
LI
and I
LO
values for DDP on Chater 4.3
1. Corrected the errata
2. Added Data Protection flow chart.
3. Removed Cache Read Operation.
4. Added additional information on command register.
5. Revised Interrupt status register information.
6. Added INT pin schematic.
7. Changed tPGM1 to 205 from 320us, tPGM2 to 220 from 350us.
8. Revised AC/DC parameters
9. Revised ECC Bypass Description
10. Revised Reset Parameters and Timing Diagrams.
1. Corrected the errata.
2. Revised Data Protection Flow Chart.
3. Revised Invalid Block Table Creation Flow Chart.
4. Revised Multi Block Erase Description.
5. Revised Device Bus Operation.
6. Revised Reset Mode Operation.
FLASH MEMORY
Draft Date
Feb. 28, 2005
Remark
Preliminary
1.0
May. 17, 2005
Final
1.1
Aug. 11, 2005
Final
1.2
Dec. 23, 2005
1. Corrected the errata.
2. Chapter 2.8.11 & 2.8.23 : Added comments about setting DFS.
3. Chapter 3.4.4 & 3.6 & 3.9 & 3.9.1 & 3.10.1 & 3.10.3 & 3.10.4 & 3.11.1 &
3.11.2 & 3.11.3 : Changed DBS setting step of the flow chart.
4. Chapter 5.7 : Modified a parameter name from ’WE Pulse Width’ to ’WE
Pulse Width Low’.
5. Chapter 6.8 : Corrected ’Block Erase Operation Timing’.
6. Chpater 7.1.1 & 7.1.2 : Modified description and pin connection.
Final
4
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
1.2
Flash Product Type Selector
Samsung offers a variety of Flash solutions including NAND Flash, MuxOneNAND
™
and NOR Flash. Samsung offers Flash products
both component and a variety of card formats including RS-MMC, MMC, CompactFlash, and SmartMedia.
To determine which Samsung Flash product solution is best for your application, refer the product selector chart.
Application Requires
Fast Random Read
Fast Sequential Read
Fast Write/Program
Multi Block Erase
Erase Suspend/Resume
Copyback
Lock/Unlock/Lock-Tight
ECC
Scalability
Samsung Flash Products
NAND
•
•
MuxOneNAND
™
•
•
•
(Max 64 Blocks)
•
•
(EDC)
External (Hardware/Software)
•
•
(ECC)
•
Internal
•
•
X
•
•
NOR
•
1.3
Ordering Information
K F M 1G 1 6 Q 2 M - D E B 5
Speed
5 : 54MHz
6 : 66MHz
Product Line desinator
B : Include Bad Block
D : Daisy Sample
Operating Temperature Range
E = Extended Temp. (-30
°C
to 85
°C)
Package
D : FBGA(Lead Free)
Version
1st Generation
Page Architecture
2 : 2KB Page
Samsung
MuxOneNAND Mem-
Device Type
M : Single Chip
N : Dual Chip
Density
1G : 1Gb
2G : 2Gb
Organization
x16 Organization
Operating Voltage Range
Q : 1.8V(1.7 V to 1.95V)
5
