KM6264B Family
8Kx8 bit Low Power CMOS Static RAM
FEATURE SUMMARY
•
Process Technology : CMOS
•
Organization : 8K x 8
•
Power Supply Voltage : Single 5V ± 10%
•
Low Data Retention Voltage : 2V(Min)
•
Three state output and TTL Compatible
•
Package Type : JEDEC Standard
28-DIP, 28-SOP
CMOS SRAM
GENERAL DESCRIPTION
The KM6264B family is fabricated by SAMSUNG's
advanced CMOS process technology. The family
can support various operating temperature ranges
and has various package types for user flexibility of
system design. The family also support low data
retention voltage for battery back-up operations with
low data retention current.
PRODUCT FAMILY
Product
Family
KM6264BL
KM6264BL-L
KM6264BLE
KM6264BLE-L
KM6264BLI
KM6264BLI-L
Operating
Temperature
Commercial
(0~70 °C)
Extended
(-25~-85 °C)
Industrial
(-40~85 °C)
Speed
PKG Type
Power Dissipation
Standby(Isb1, Max) Operating(Icc2)
100uA
70/100/120ns 28-DIP, 28-SOP
100*ns
100*ns
28-SOP
28-SOP
10uA
100uA
50uA
100uA
50uA
55mA
* measured with 30pF test load
PIN DESCRIPTION
N.C
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
Vcc
/WE
FUNCTIONAL BLOCK DIAGRAM
Y-Decoder
X-Decoder
Control Logic
CS2
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
Cell Array
A0~A12
28-Pin DIP
28-Pin SOP
22
21
20
19
18
17
16
15
I/O1~8
I/O Buffer
Function
/CS1, CS2
/WE, /OE
Pin Name
A0~A12
/WE
/CS1, CS2
/OE
I/O1~I/O8
Vcc
Vss
N.C
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Input/Output
Power(5V)
Ground
No Connection
1
ELECTRONICS
Revision. 0.0
Auust. 1996
KM6264B Family
PRODUCT LIST & ORDERING INFORMATION
PRODUCT LIST
Commercial Temp Products
(0~70 °C)
Part Name
KM6264BLP-7
KM6264BLP-7L
KM6264BLP-10
KM6264BLP-10L
KM6264BLP-12
KM6264BLP-12L
KM6264BLG-7
KM6264BLG-7L
KM6264BLG-10
KM6264BLG-10L
KM6264BLG-12
KM6264BLG-12L
CMOS SRAM
Extended Temp Products
(-25~85 °C)
Part Name
KM6264BLGE-10
KM6264BLGE-10L
Industrial Temp Products
(-40~85 °C)
Part Name
KM6264BLGI-10
KM6264BLGI-10L
Function
28-DIP, 70ns, L-pwr
28-DIP, 70ns, , LL-pwr
28-DIP, 100ns, , L-pwr
28-DIP, 100ns, LL-pwr
28-DIP, 120ns, , L-pwr
28-DIP, 120ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr
28-SOP, 120ns, L-pwr
28-SOP, 120ns, LL-pwr
Function
28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr
Function
28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr
ORDERING INFORMATION
K M6 2 X 64
B
X
X
XX -
XX
X
L-Low Low Power, Blank-Low Power or High Power
Access Time : 7=70ns, 10=100ns, 12=120ns
Operating Temperature :
I=Industrial, E=Extended, Blank=Commercial
Package Type : G=SOP, P=DIP,
L-Low Power or Low Low Power, Blank-High Power
Die Version : B=3rd generation
Density : 64=64K bit
Blank=5V
Organization : 2= x8
SEC Standard SRAM
2
ELECTRONICS
Revision. 0.0
Auust. 1996
KM6264B Family
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
Vin, Vout
Vcc
Pd
Tstg
Ta
Ratings
-0.5 to Vcc+0.5
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-25 to 85
-40 to 85
Soldering temperature and time
Tsolder
260 °C, 10sec(Lead Only)
Unit
V
V
W
°C
°C
°C
°C
-
CMOS SRAM
Remark
-
-
-
-
KM6264BL/L-L
KM6264BLE/LE-L
KM6264BLI/LI-L
-
* Stresses greater than those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
Vih
Vil
Min
4.5
0
2.2
-0.5***
Typ**
5.0
0
-
-
Max
5.5
0
Vcc+0.5
0.8
Unit
V
V
V
V
* 1) Commercial Product : Ta=0 to 70 ° C, unless otherwise specified
2) Extended Product : Ta=-25 to 85 ° C, unless otherwise specified
3) Industrial Product : Ta=-40 to 85 ° C, unless otherwise specified
** Ta=25 ° C
*** Vil(min)=-3.0V for
¡ Â
0ns pulse
5
CAPACITANCE *
(f=1MHz, Ta=25 °C)
Item
Input capacitance
Input/Output capacitance
Symbol
Cin
Cio
Test Condition
Vin=0V
Vio=0V
Min
-
-
Max
6
8
Unit
pF
pF
* Capacitance is sampled not 100% tested
3
ELECTRONICS
Revision. 0.0
Auust. 1996
KM6264B Family
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Symbol
Ili
Ilo
Icc
Icc1
Test Conditions*
Vin=Vss to Vcc
/CS1=Vih or CS2=Vil or /WE=Vil
Vi/o=Vss to Vcc
/CS1=Vil, CS2=Vih
Vin=Vil or Vih, Ii/o=0mA
Cycle time=1us, 100% duty
/CS1
¡ Â
.2V, CS2
¡ Ã
cc-0.2V
0
V
Icc2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby
Current
(CMOS)
KM6264BL
KM6264BL-L
KM6264BLE
KM6264BLE-L
KM6264BLI
KM6264BLI-L
* 1) Commercial Product : Ta=0 to 70 ° C, Vcc=5V+/-10%, unless otherwise specified
2) Extended Product : Ta=-25 to 85 ° C, Vcc=5V+/-10%, unless otherwise specified
3) Industrial Product : Ta=-40 to 85 ° C, Vcc=5V+/-10%, unless otherwise specified
** Ta=25 ° C
CMOS SRAM
Min
-1
-1
-
-
Typ**
-
-
7
-
Max
1
1
15
10
Unit
uA
uA
mA
mA
Min cycle, 100% duty
/CS1=Vil, CS2=Vih, Ii/o=0mA
Iol=2.1mA
Ioh= -1.0mA
/CS1=Vih or CS2=Vil
/CS1
¡ Ã
cc-0.2V
V
CS2
¡ Ã
cc-0.2V or
V
CS2
¡ Â
.2V
0
Others 0~Vcc
L
LL
L
LL
L
LL
-
-
2.4
-
-
-
-
-
-
-
-
-
-
-
2
1
-
-
-
-
55
0.4
-
1
100
10
100
50
100
50
mA
V
V
mA
uA
uA
uA
uA
uA
uA
Vol
Voh
Isb
Isb1
A.C CHARACTERISTICS
TEST CONDITIONS
(
1. Test Load and Test Input/Output Reference)
*
Item
Input pulse level
Input rise fall time
Value
0.8 to 2.4V
5ns
Remark
-
-
-
-
* Including scope and jig capacitance
* See test condition of DC and AC Operating characteristics
C
L
*
Input and output reference voltage 1.5V
Output load(See right)
C
L
=100pF+1TTL
4
ELECTRONICS
Revision. 0.0
Auust. 1996
KM6264B Family
TEST CONDITIONS
(2. Temperature and Vcc Conditions)
Product Family
KM6264BL/L-L
KM6264BLE/LE-L
KM6264BLI/LI-L
* measured with 30pF test load
CMOS SRAM
Temperature
0~70 °C
-25~85 °C
-40~85 °C
Power Supply(Vcc)
5V +/- 10%
5V +/- 10%
5V +/- 10%
Speed Bin
70/100/120ns
100*ns
100*ns
Comments
Commercial
Extended
Industrial
PARAMETER LIST FOR EACH SPEED BIN
Speed Bins
Parameter List
Read
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Symbol
70
-
-
-
5
5
0
0
10
70
60
0
60
40
0
0
30
0
5
70ns
Min
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
Max
-
70
70
35
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
100ns
Min
100
-
-
-
10
5
0
0
10
100
80
0
80
60
0
0
40
0
5
Max
-
100
100
50
-
-
35
35
-
-
-
-
-
-
-
30
-
-
-
120ns
Min
120
-
-
-
10
5
0
0
10
120
85
0
85
70
0
0
50
0
10
Max
-
120
120
60
-
-
40
40
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Output hold from address change tOH
Write
Write cycle time
tWC
Chip select to end of write
tCW
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
5
ELECTRONICS
Revision. 0.0
Auust. 1996
瑞萨电子MCU
