KM736V887
KM718V987
Document Title
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No.
0.0
0.1
History
Initial draft
Change DC Characteristics.
I
SB
value from 60mA to 90mA at -8
I
SB
value from 50mA to 80mA at -9
I
SB
value from 40mA to 70mA at -10
I
SB1
value from 10mA to 30mA
I
SB2
value from 10mA to 30mA
1. Changed t
CD
from 8.0ns to 8.5ns at -8
2. Changed t
CYC
from 13.0ns to 12.0ns at -10
3. Changed DC condition at Icc and parameters
I
CC
; from 300mA to 350mA at -8,
from 260mA to 300mA at -9,
from 220mA to 260mA at -10,
I
SB
; from 90mA to 130mA at -8,
from 80mA to 120mA at -9,
from 70mA to 110mA at -10,
1. A
DD
119BGA(7x17 Ball Grid Array Package) .
2. A
DD
x32 organization.
Add V
DDQ
Supply voltage( 2.5V )
Changed V
OL
Max value from 0.2V to 0.4V at 2.5V I/O.
1. Final Spec Release.
2. Remove x32 organization.
1. Remove V
DDQ
supply voltage(2.5V)
1. Changed I
CC
from 350mA to 330mA at -8.
2. Add bin -7. (tCD 7.5ns).
1. Add V
DDQ
supply voltage(2.5V)
1. Changed tCYC from 12ns to 10ns at -9.
Draft Date
April. 10 . 1998
Aug. 31. 1998
Remark
Preliminary
Preliminary
0.2
Sep. 09. 1998
Preliminary
0.3
Oct. 15. 1998
Preliminary
0.4
0.5
1.0
Dec. 10. 1998
Dec. 23. 1998
Jan. 29. 1999
Preliminary
Preliminary
Final
2.0
3.0
Feb. 25. 1999
Mar. 30. 1999
Final
Final
4.0
5.0
May. 13. 1999
Nov. 19. 1999
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
November 1999
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package)
GENERAL DESCRIPTION
The KM736V887 and KM718V987 are 9,437,184-bit Synchro-
nous Static Random Access Memory designed for high perfor-
mance second level cache of Pentium and Power PC based
System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM736V887 and KM718V987 are fabricated using SAM-
SUNG′s high performance CMOS technology and is available
in a 100pin TQFP and 119BGA package. Multiple power and
ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -7
t
CYC
t
CD
t
OE
8.5
-8
10
-9
10
-10 Unit
12
ns
7.5 8.5 9.0 10.0 ns
3.5 3.5 3.5 3.5
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
17
or A
0
~A
18
ADDRESS
REGISTER
A
2
~A
17
or A
2
~A
18
A′
0
~A′
1
256Kx36 , 512Kx18
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa,DQPb
-2-
November 1999
Rev 5.0
KM736V887
KM718V987
PIN CONFIGURATION
(TOP VIEW)
256Kx36 & 512Kx18 Synchronous SRAM
ADSC
ADSP
WEd
WEb
WEa
WEc
ADV
83
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
17
A
10
A
11
A
12
A
13
A
14
A
15
PIN
SYMBOL
A
0
- A
17
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
15,41,65,91
17,40,67,90
14,16,38,39,42,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
32,33,34,35,36,37,43
44,45,46,47,48,49,50
81,82,99,100
ADV
Burst Address Advance
83
ADSP
Address Status Processor 84
ADSC
Address Status Controller 85
CLK
Clock
89
CS
1
Chip Select
98
CS
2
Chip Select
97
CS
2
Chip Select
92
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
GW
Global Write Enable
88
BW
Byte Write Enable
87
ZZ
Power Down Input
64
LBO
Burst Mode Control
31
LBO
V
SS
Output Power Supply
(2.5V or 3.3V)
Output Ground
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
A
16
50
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
81
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
KM736V887(256Kx36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
-3-
November 1999
Rev 5.0
KM736V887
KM718V987
PIN CONFIGURATION
(TOP VIEW)
256Kx36 & 512Kx18 Synchronous SRAM
ADSC
ADSP
WEb
WEa
ADV
83
N.C.
N.C.
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
18
A
11
A
12
A
13
A
14
A
15
A
16
PIN NAME
SYMBOL
A
0
- A
18
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,43
44,45,46,47,48,49,50
80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,51,52,53,56,
57,66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
V
SS
DQa
0
~ a
7
DQb
0
~ b
7
DQPa, Pb
V
DDQ
V
SSQ
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
0
DQb
1
V
SSQ
V
DDQ
DQb
2
DQb
3
N.C.
V
DD
N.C.
V
SS
DQb
4
DQb
5
V
DDQ
V
SSQ
DQb
6
DQb
7
DQPb
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
KM718V987(512Kx18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQPa
DQa
7
DQa
6
V
SSQ
V
DDQ
DQa
5
DQa
4
V
SS
N.C.
V
DD
ZZ
DQa
3
DQa
2
V
DDQ
V
SSQ
DQa
1
DQa
0
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
-4-
November 1999
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
119BGA PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
KM736V887(256Kx36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
CS2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
NC
3
A
A
A
V
SS
V
SS
V
SS
WEc
V
SS
NC
V
SS
WEd
V
SS
V
SS
V
SS
LBO
A
NC
4
ADSP
ADSC
V
DD
NC
CS
1
OE
ADV
GW
V
DD
CLK
NC
BW
A
1
*
A
0
*
V
DD
A
NC
5
A
A
A
V
SS
V
SS
V
SS
WEb
V
SS
NC
V
SS
WEa
V
SS
V
SS
V
SS
NC
A
NC
6
A
A
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Note :
* A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
A
A
0
, A
1
ADV
ADSP
ADSC
CLK
CS
1
CS
2
WEx
(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
PIN NAME
Address Inputs
Burst Count Address
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Byte Write Inputs
V
DD
V
SS
N.C.
DQa
DQb
DQc
DQd
DQPa~Pd
V
DDQ
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
SYMBOL
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
Output Power Supply
(2.5V or 3.3V)
-5-
November 1999
Rev 5.0
