Advance Information
MC9328MXL/D
Rev. 3.1, 6/2003
MC9328MXL
i.MX Integrated Portable
System Processor
Contents
1 Introduction . . . . . . . . . . . 1
2 Signals and
Connections . . . . . . . . . . 4
3 Specifications . . . . . . . . 10
4 Pin-Out and Package
Information . . . . . . . . . . 78
1 Introduction
The i.MX family builds on the DragonBall family of application processors which have
demonstrated leadership in the portable handheld market. Continuing this legacy, the i.MX
(Media Extensions) series provides a leap in performance with an ARM9™ microprocessor
core and highly integrated system functions. The i.MX products specifically address the
requirements of the personal, portable product market by providing intelligent integrated
peripherals, an advanced processor core, and power management capabilities.
The new MC9328MXL features the advanced and power-efficient ARM920T™ core that
operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller,
USB support, and an MMC/SD host controller, support a suite of peripherals to enhance any
product seeking to provide a rich multimedia experience. It is packaged in either a 256-pin
Mold Array Process-Ball Grid Array (MAPBGA) or 225-pin PBGA package. Figure 1 shows
the functional block diagram of the MC9328MXL.
System Control
JTAG/ICE
Bootstrap
Standard
System I/O
GPIO
Connectivity
MMC/SD
CPU Complex
Memory Stick®
Host Controller
ARM9TDMI™
SPI 1 and
SPI 2
UART 1
UART 2
SSI/I2S
I2C
USB Device
AIPI 2
DMAC
(11 Chnl)
EIM &
SDRAMC
Bus
Control
Human Interface
LCD Controller
I Cache
D Cache
RTC
Watchdog
Power
Control
CGM
(PLLx2)
MC9328MXL
PWM
Timer 1 & 2
Multimedia
Multimedia
Accelerator
Video Port
AIPI 1
VMMU
Interrupt
Controller
Figure 1. MC9328MXL Functional Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change
without notice. © Motorola, Inc., 2003. All rights reserved.
Introduction
1.1 Conventions
This document uses the following conventions:
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OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one
is a voltage that corresponds to Boolean true (1) state.
Logic level zero
is a voltage that corresponds to Boolean false (0) state.
To
set
a bit or bits means to establish logic level one.
To
clear
a bit or bits means to establish logic level zero.
A
signal
is an electronic construct whose state conveys or changes in state convey information.
A
pin
is an external physical connection. The same pin can be used to connect a number of signals.
Asserted
means that a discrete signal is in active logic state.
—
Active low
signals change from logic level one to logic level zero.
—
Active high
signals change from logic level zero to logic level one.
•
Negated
means that an asserted discrete signal changes logic state.
—
Active low
signals change from logic level zero to logic level one.
—
Active high
signals change from logic level one to logic level zero.
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•
LSB means
least significant bit
or
bits,
and MSB means
most significant bit
or
bits.
References to
low and high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or
0x
are hexadecimal.
1.2 Features
To support a wide variety of applications, the MC9328MXL offers a robust array of features, including the
following:
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ARM920T™ Microprocessor Core
AHB to IP Bus Interfaces (AIPIs)
External Interface Module (EIM)
SDRAM Controller (SDRAMC)
DPLL Clock and Power Control Module
Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)
Two Serial Peripheral Interfaces (SPI1 and SPI2)
Two General-Purpose 32-bit Counters/Timers
Watchdog Timer
Real-Time Clock/Sampling Timer (RTC)
LCD Controller (LCDC)
Pulse-Width Modulation (PWM) Module
Universal Serial Bus (USB) Device
Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
Memory Stick® Host Controller (MSHC)
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MC9328MXL Advance Information
MOTOROLA
Introduction
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Direct Memory Access Controller (DMAC)
Synchronous Serial Interface and Inter-IC Sound (SSI/I
2
S) Module
Inter-IC (I
2
C) Bus Module
Video Port
General-Purpose I/O (GPIO) Ports
Bootstrap Mode
Multimedia Accelerator (MMA)
Power Management Features
Operating Voltage Range: 1.7 V to 1.98 V core, 1.7 V to 3.3V I/O
256-pin MAPBGA Package
225-pin MAPBGA Package
1.3 Target Applications
The MC9328MXL is targeted for advanced information appliances, smart phones, Web browsers, digital
MP3 audio players, handheld computers, and messaging applications.
1.4 Product Documentation
The following documents are required for a complete description of the MC9328MXL and are necessary to
design properly with the device. Especially for those not familiar with the ARM920T processor or
previous DragonBall products, the following documents are helpful when used in conjunction with this
document.
ARM Architecture Reference Manual
(ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual
(ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual
(ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual
(ARM Ltd., order number DDI O157E)
MC9328MXL Product Brief
(order number MC9328MXLP/D)
MC9328MXL Reference Manual
(order number MC9328MXLRM/D)
The Motorola manuals are available on the Motorola Semiconductors Web site at
http://www.motorola.com/semiconductors. These documents may be downloaded directly from the
Motorola Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from
http://www.arm.com.
MOTOROLA
MC9328MXL Advance Information
3
Signals and Connections
1.5 Ordering Information
Table 1 provides ordering information for both the 256-lead mold array process ball grid array
(MAPBGA) package and the 225-lead BGA package.
Table 1. MC9328MXL Ordering Information
Package Type
Frequency
Temperature
0
O
C to 70
O
C
Pb-free
150 MHz
-30
O
C to 70
O
C
Pb-free
256-lead MAPBGA
-40
O
C to 85
O
C
Pb-free
0
O
C to 70
O
C
Pb-free
200 MHz
MC9328MXLDVH20
-30
O
C to 70
O
C
Pb-free
0
O
C to 70
O
C
Pb-free
150 MHz
-30
O
C to 70
O
C
Pb-free
225-lead MAPBGA
-40
O
C to 85
O
C
Pb-free
0
O
C to 70
O
C
Pb-free
200 MHz
MC9328MXLDVF20
-30
O
C to 70
O
C
Pb-free
MC9328MXLDVP20
MC9328MXLVP20
MC9328MXLCVP15
MC9328MXLVF20
MC9328MXLDVP15
MC9328MXLCVF15
MC9328MXLVP15
MC9328MXLDVF15
MC9328MXLDVM20
MC9328MXLVF15
MC9328MXLVM20
MC9328MXLCVM15
MC9328MXLVH20
MC9328MXLDVM15
MC9328MXLCVH15
MC9328MXLVM15
MC9328MXLDVH15
Solderball Type
Order Number
MC9328MXLVH15
2 Signals and Connections
Table 2 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 2. MC9328MXL Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip-Select (EIM)
A[24:0]
D[31:0]
EB0
Address bus signals
Data bus signals
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
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MC9328MXL Advance Information
MOTOROLA
Signals and Connections
Table 2. MC9328MXL Signal Descriptions (Continued)
Signal Name
EB1
EB2
EB3
OE
CS [5:0]
Function/Notes
Byte Strobe—Active low external enable byte signal that controls D [23:16].
Byte Strobe—Active low external enable byte signal that controls D [15:8].
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
Memory Output Enable—Active low output enables external data bus.
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are
selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is
selected.
Active low input signal sent by a flash device to the EIM whenever the flash device must
terminate an on-going burst sequence and initiate a new (long first access) burst
sequence.
Active low signal sent by a flash device causing the external burst device to latch the
starting burst address.
Clock signal sent to external synchronous memories (such as burst flash) during burst
mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used
as a WE input signal by external DRAM.
DTACK signal—
The external input data acknowledge signal. When using the external
DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus
error when a bus cycle is not terminated by the external DTACK signal after 1022 clock
counts have elapsed.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the MC9328MXL upon
system reset is determined by the settings of these pins.
SDRAM Controller
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals
A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in
SDRAM/SyncFlash cycles.
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address
signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in
SDRAM/SyncFlash cycles.
SDRAM address signals
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0]
are selected on SDRAM/SyncFlash cycles.
SDRAM data enable
SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These
two signals are selectable by programming the system control register.
SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two
signals are selectable by programming the system control register. By default, CSD1 is
selected, so it can be used as SyncFlash boot chip-select by properly configuring BOOT
[3:0] input pins.
SDRAM/SyncFlash Row Address Select signal
ECB
LBA
BCLK
RW
DTACK
SDBA [4:0]
SDIBA [3:0]
MA [11:10]
MA [9:0]
DQM [3:0]
CSD0
CSD1
RAS
MOTOROLA
MC9328MXL Advance Information
5
