DRAM MODULE
KMM372F213CK/CS EDO Mode
2M x 72 DRAM DIMM with ECC using 2Mx8, 2K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung KMM372F213C is a 2Mx72bits Dynamic RAM
high density memory module. The Samsung KMM372F213C
consists of nine CMOS 2Mx8bits DRAMs in SOJ/TSOP-II
300mil package, and two 16bits driver IC in 48pin TSSOP
package mounted on a 168-pin glass-epoxy substrate. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit
board for each DRAM. The KMM372F213C is a Dual In-line
Memory Module and is intended for mounting into 168-pin
edge connector sockets.
KMM372F213CK/CS
FEATURES
• Part Identification
- KMM372F213CK (2048 cycles/32ms Ref., SOJ)
- KMM372F213CS (2048 cycles/32ms Ref., TSOP)
• Fast Page Mode with Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single 3.3V±0.3V power supply
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
18ns
20ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
• PCB : Height(1000mil), Single sided component
PIN CONFIGURATIONS
Pin Front Pin Front Pin Front Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
RSVD
RSVD
V
CC
W0
CAS0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
RSVD
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
*A12
V
CC
RFU
RFU
V
SS
OE2
RAS2
CAS4
RSVD
W2
V
CC
RSVD
RSVD
DQ18
DQ19
V
SS
DQ20
DQ21
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ22
DQ23
V
CC
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
DQ35
V
SS
PD1
PD3
PD5
PD7
ID0
V
CC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
DQ53
V
SS
RSVD
RSVD
V
CC
RFU
*CAS1
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
RSVD
*RAS1
RFU
V
SS
A1
A3
A5
A7
A9
*A11
*A13
V
CC
RFU
B0
V
SS
RFU
*RAS3
*CAS5
RSVD
PDE
V
CC
RSVD
RSVD
DQ54
DQ55
V
SS
DQ56
DQ57
Pin Back
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ58
DQ59
V
CC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2
PD4
PD6
PD8
ID1
V
CC
PIN NAMES
Pin Names
A0, B0, A1 - A10
DQ0 - DQ71
W0, W2
OE, OE2
RAS0, RAS2
CAS0, CAS4
V
CC
V
SS
NC
PDE
PD1 - 8
ID0 - 1
RSVD
RFU
Function
Address Input
Data In/Out
Read/Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power(+3.3V)
Ground
No Connection
Presence Detect Enable
Presence Detect
ID bit
Reserved Use
Reserved for Future Use
Pins marked
′*′
are not used in this module.
PD & ID Table
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
ID0
ID1
50NS
1
0
0
1
1
0
0
0
0
0
60NS
1
0
0
1
1
1
1
0
0
0
PD Note : PD & ID Terminals must each be pulled up through a resister to V
CC
at the next higher
level assembly. PDs will be either open (NC) or driven to V
SS
via on-board buffer circuits.
PD : 0 for Vol of Drive IC & 1 for N.C
ID Note : IDs will be either open (NC) or connected directly to V
SS
without a buffer.
ID : 0 for Vss & 1 for N.C
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS0
CAS0
W0
OE0
A0
A1-A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vcc
0.1 or 0.22uF Capacitor
under each DRAM
Vss
To all DRAMs
RAS2
CAS4
W2
OE2
B0
A1-A10
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
KMM372F213CK/CS
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U5
U1
U6
U2
U7
U3
U8
U4
A0
B0
A1-An
W0, 2
OE0, 2
U0-U4
U5-U8
A1-An : U0-U8
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
KMM372F213CK/CS
Rating
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
9
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
CC
+1.3V/15ns, Pulse width is measured at V
CC
.
*2 : -1.3V/15ns, Pulse width is measured at V
SS
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3
*2
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
*1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM372F213CK/CS
Min
-
-
Max
990
900
100
990
900
810
720
30
990
900
25
5
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-25
-5
2.4
-
I
CC1
* : Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
* : EDO Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
I
CC5
: Standby Current (RAS=CAS=W=Vcc-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I
I(L)
: Input Leakage Current (Any input 0≤V
IN
≤Vcc+0.3V,
all other pins not under test=0 V)
I
O(L)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤Vcc)
V
OH
: Output High Voltage Level (I
OH
= -2mA)
V
OL
: Output Low Voltage Level (I
OL
= 2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one hyper page mode cycle,
t
HPC
.
DRAM MODULE
CAPACITANCE
(T
A
= 25°C, Vcc=3.3V, f = 1MHz)
Item
Input capacitance[A0-A10, B0]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0, CAS4]
Input/Output capacitance[DQ0 - 71]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
Min
-
-
-
-
-
KMM372F213CK/CS
Max
20
20
45
20
20
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=3.3V±0.3V. See notes 1,2.)
Test condition : V
ih
/V
il
=2.0/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
OE to output in Low-Z
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
Refresh period(2K Ref.)
Write command set-up time
CAS to W delay time
RAS to W delay time
Symbol
Min
-5
Max
Min
104
155
50
18
30
8
8
8
2
30
50
18
36
8
18
13
10
5
8
0
8
30
0
0
-2
10
10
18
8
-2
13
32
0
36
71
0
40
83
10K
32
20
10K
18
50
8
8
8
2
40
60
20
43
10
18
13
10
5
8
0
10
35
0
0
-2
10
10
20
10
-2
15
32
10K
40
25
10K
20
50
60
20
35
84
131
-6
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
7
7
7,14
9,14
9,14
14
8
8,14
14
14
14
13
4,14
10,14
14
14
14
3,4,10
3,4,5,14
3,10,14
3,14
3,14
6,11,12,14
2
Unit
Note
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
OLZ
t
CEZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CWD
t
RWD
DRAM MODULE
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=3.3V±0.3V. See notes 1,2.)
Test condition : V
ih
/V
il
=2.0/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Column address to W delay time
CAS precharge time to W delay time
CAS set-up time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper page cycle time
Hyper page read-modify-write cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay time from RAS
Output buffer turn off delay time from W
W to data delay
OE to CAS hold time
CAS hold time to OE
OE precharge time
W pulse width(Hyper page cycle)
Present Detect Read Cycle
PDE to Valid PD bit
PDE to PD bit Inactive
Symbol
-5
Min
48
53
5
8
3
33
20
68
8
50
35
18
18
5
13
15
8
10
3
3
20
5
5
5
5
13
18
18
20
5
15
15
8
10
3
3
20
5
5
5
5
200K
25
77
10
60
40
Max
Min
55
60
5
8
3
KMM372F213CK/CS
-6
Max
Unit
ns
ns
ns
ns
ns
Note
7
14
14
14
3,14
12
12
t
AWD
t
CPWD
t
CSR
t
CHR
t
RPC
t
CPA
t
HPC
t
HPRWC
t
CP
t
RASP
t
RHCP
t
OEA
t
OED
t
OEZ
t
OEH
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
OCH
t
CHO
t
OEP
t
WPE
40
ns
ns
ns
ns
200K
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
14
14
6.11.12
6.11.14
14
14
14
14
6,11,14
15
20
ns
ns
ns
ns
ns
ns
ns
t
PD
t
PDOFF
10
2
7
2
10
7
ns
ns
