Freescale Semiconductor
Technical Data
MPC8540EC
Rev. 4.1, 07/2007
MPC8540
Integrated Processor
Hardware Specifications
The MPC8540 integrates a PowerPC™ processor core built
on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8540 is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the
MPC8540
PowerQUICC III Integrated Host Processor Reference
Manual.
To locate any published errata or updates for this document,
contact your Freescale sales office.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Three-Speed,10/100, MII Management . . 22
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 66
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
System Design Information . . . . . . . . . . . . . . . . . . . 88
Document Revision History . . . . . . . . . . . . . . . . . . . 95
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 100
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© Freescale Semiconductor, Inc., 2004-2007. All rights reserved.
Overview
1 Overview
The following section provides a high-level overview of the MPC8540 features.
Figure 1
shows the major
functional units within the MPC8540.
DDR
SDRAM
ROM,
SDRAM,
GPIO
IRQs
DDR SDRAM Controller
256KB
L2-Cache/
SRAM
e500
Coherency
Module
e500 Core
32 KB L1
I Cache
32 KB L1
D Cache
Local Bus Controller
Programmable
Interrupt Controller
Core Complex Bus
RapidIO Controller
OCeaN
MII
10/100
ENET
PCI/PCI-X Controller
4ch DMA Controller
Serial
DUART
TSEC
I
2
C
I
2
C
Controller
10/100/1G
RapidIO-8
16 Gb/s
PCI-X 64b
133 MHz
MII, GMII,TBI,
RTBI, RGMII
TSEC
10/100/1G
MII, GMII,TBI,
RTBI, RGMII
Figure 1. MPC8540 Block Diagram
1.1 Key Features
The following lists an overview of the MPC8540 feature set.
• High-performance, 32-bit Book E–enhanced core that implements the Power Architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis. Separate locking for instructions and data
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the MPC8540 performance monitor
described in Chapter 18, “Performance Monitor.”
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Overview
•
•
•
256 Kbyte L2 cache/SRAM
— Can be configured as follows
– Full cache mode (256-Kbyte cache).
– Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte
block or two 128-Kbyte blocks)
– Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped
SRAM)
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing)
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines. Individual line locks are set and cleared
through Book E instructions or by externally mastered transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
— SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global)
– Regions can reside at any aligned location in the memory map
– Byte accessible ECC is protected using read-modify-write transactions accesses for smaller
than cache-line accesses.
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI/PCI-X
– Four inbound windows plus a default and configuration window on RapidIO
– Four outbound windows plus default translation for PCI
– Eight outbound windows plus default translation for RapidIO
DDR memory controller
— Programmable timing supporting DDR-1 SDRAM
— 64-bit data interface, up to 333-MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
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Overview
•
•
•
— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
RapidIO interface unit
— 8-bit RapidIO I/O and messaging protocols
— Source-synchronous double data rate (DDR) interfaces
— Supports small type systems (small domain, 8-bit device ID)
— Supports four priority levels (ordering within a level)
— Reordering across priority levels
— Maximum data payload of 256 bytes per packet
— Packet pacing support at the physical layer
— CRC protection for packets
— Supports atomic operations increment, decrement, set, and clear
— LVDS signaling
RapidIO–compliant message unit
— One inbound data message structure (inbox)
— One outbound data message structure (outbox)
— Supports chaining and direct modes in the outbox
— Support of up to 16 packets per message
— Support of up to 256 bytes per packet and up to 4 Kbytes of data per message
— Supports one inbound doorbell message structure
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
— Four global high resolution timers/counters that can generate interrupts
— Supports 22 other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing
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Overview
•
•
•
•
•
•
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
I
2
C controller
— Two-wire interface
— Multiple master support
— Master or slave I
2
C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the I
2
C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I
2
C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
10/100 fast Ethernet controller (FEC)
— Operates at 10 to 100 megabits per second (Mbps) as a device debug and maintenance port
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit)
Two three-speed (10/100/1Gb) Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers
— Support for different Ethernet physical interfaces:
– 10/100/1Gb Mbps IEEE 802.3 GMII
– 10/100 Mbps IEEE 802.3 MII
– 10 Mbps IEEE 802.3 MII
– 1000 Mbps IEEE 802.3z TBI
– 10/100/1Gb Mbps RGMII/RTBI
— Full- and half-duplex support
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