Freescale Semiconductor
Technical Data
MSC8126
Rev. 11, 4/2006
MSC8126
Quad Core 16-Bit Digital Signal Processor
The raw processing power of
this highly integrated system-
on-a-chip device will enable
developers to create next-
generation networking
products that offer
tremendous channel
densities, while maintaining
system flexibility, scalability,
and upgradeability. The
MSC8126 is offered in two
core speed levels: 400 and
500 MHz.
SC140
Extended Core
MQBus
SC140
Extended Core
128
SQBus
SC140
Extended Core
SC140
Extended Core
128
64
IP Master
32 Timers
Memory
Controller
Banks 9, 11
UART
RS-232
Local Bus
Boot
ROM
224KB
M2
RAM
256KB
M2
RAM
4 TDMs
IPBus1
32
8 Hardware
Semaphores
GPIO
GIC
GPIO, I
2
C
Interrupts
IP Master
TCOP
IPBus2
VCOP
PLL/Clock
JTAG Port
What’s New?
Rev. 11
includes the following:
MII/RMII/SMII
PLL
JTAG
Local Bus
64
DMA
Controller
10/100
Ethernet
Controller
Direct
Slave
Interface
(DSI)
Memory
Controller
Banks 0–7
• Chapter 2
updates
Table 2-11
reset timing values.
DSI Port
32/64
System Bus
32/64
System
Interface
64
Bridge
SIU
Registers
Internal System Bus
Note:
The arrows show the direction from which the transfer originates.
Figure 1.
MSC8126 Block Diagram
The MSC8126 is a highly integrated system-on- a-chip that combines four SC140 extended cores with a turbo
coprocessor (TCOP), a Viterbi coprocessor (VCOP), an RS-232 serial interface, four time-division multiplexed
(TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), an Ethernet
interface, and a multi-channel DMA controller. The four extended cores can deliver a total 8000 DSP MMACS
performance at 500 MHz. Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and
two interrupt controllers (see
Figure 2).
The MSC8126 device targets high-bandwidth highly computational DSP
applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station
applications. The MSC8126 delivers enhanced performance while maintaining low power dissipation and greatly
reducing system cost.
© Freescale Semiconductor, Inc., 2004, 2006. All rights reserved.
Table of Contents
Table of Contents
Features...............................................................................................................................................................iii
Product Documentation ......................................................................................................................................xi
Chapter 1
Signals/Connections
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Power Signals ...................................................................................................................................................1-3
Clock Signals ....................................................................................................................................................1-3
Reset and Configuration Signals.......................................................................................................................1-3
Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals ...............................................................1-4
Memory Controller Signals ............................................................................................................................1-14
GPIO, TDM, UART, and Timer Signals.........................................................................................................1-16
Dedicated Ethernet Signals.............................................................................................................................1-23
EOnCE Event and JTAG Test Access Port Signals ........................................................................................1-24
Reserved Signals.............................................................................................................................................1-24
Maximum Ratings.............................................................................................................................................2-1
Recommended Operating Conditions...............................................................................................................2-2
Thermal Characteristics ....................................................................................................................................2-3
DC Electrical Characteristics............................................................................................................................2-3
AC Timings.......................................................................................................................................................2-4
Package Description .........................................................................................................................................3-1
MSC8126 Package Mechanical Drawing .......................................................................................................3-20
Chapter 2
Specifications
2.1
2.2
2.3
2.4
2.5
Chapter 3
Packaging
3.1
3.2
Chapter 4
Design Considerations
4.1
4.2
4.3
4.4
4.5
Start-up Sequencing Recommendations ...........................................................................................................4-1
Power Supply Design Considerations...............................................................................................................4-1
Connectivity Guidelines ...................................................................................................................................4-3
External SDRAM Selection..............................................................................................................................4-4
Thermal Considerations....................................................................................................................................4-5
Data Sheet Conventions
OVERBAR
Used to indicate a signal that is active when pulled low (For example, the
RESET
pin is active
when low.)
“asserted”
Means that a high true (active high) signal is high or that a low true (active low) signal is low
“deasserted”
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Examples:
Signal/Symbol
Logic State
Signal State
Voltage
PIN
True
Asserted
V
IL
/
V
OL
PIN
False
Deasserted
V
IH
/
V
OH
PIN
True
Asserted
V
IH
/
V
OH
PIN
False
Deasserted
V
IL
/
V
OL
Note:
Values for
V
IL
,
V
OL
,
V
IH
, and
V
OH
are defined by individual product specifications.
MSC8126 Technical Data, Rev. 11
ii
Freescale Semiconductor
Features
Program
Sequencer
SC140
Core
JTAG
Power
Management
Address
Register
File
Address
ALU
EOnCE
Data ALU
Register
File
Data
ALU
SC140 Core
Xa
Xb
P
64
64
128
M1
RAM
Instruction
Cache
QBus
128
PIC
IRQs
LIC
QBus
Bank 1
QBus
Bank 3
QBC
QBus
Interface
IRQs
MQBus
SQBus
Local Bus
128
128
64
Notes: 1.
The arrows show the data transfer direction.
2.
The QBus interface includes a bus switch, write buffer, fetch unit, and a
control unit that defines four QBus banks. In addition, the QBC handles internal
memory contentions.
Figure 2.
SC140 Extended Core Block Diagram
Features
The tables in this section list the features of the MSC8126 device.
MSC8126 Technical Data, Rev. 11
Freescale Semiconductor
iii
Features
Table 1.
Extended SC140 Cores and Core Memories
Feature
Description
Four SC140 cores:
• Up to 8000 MMACS using 16 ALUs running at up to 500 MHz.
• A total of 1436 KB of internal SRAM (224 KB per core + 16 KB ICache per core + the shared M2
memory).
Each SC140 core provides the following:
• Up to 2000 MMACS using an internal 500 MHz clock. A MAC operation includes a multiply-
accumulate command with the associated data move and pointer update.
• 4 ALUs per SC140 core.
• 16 data registers, 40 bits each.
• 27 address registers, 32 bits each.
• Hardware support for fractional and integer data types.
• Very rich 16-bit wide orthogonal instruction set.
• Up to six instructions executed in a single clock cycle.
• Variable-length execution set (VLES) that can be optimized for code density and performance.
• JTAG port complies with
IEEE®
Std 1149.1™.
• Enhanced on-device emulation (EOnCE) with real-time debugging capabilities.
Each SC140 core is embedded within an extended core that provides the following:
• 224 KB M1 memory that is accessed by the SC140 core with zero wait states.
• Support for atomic accesses to the M1 memory.
• 16 KB instruction cache, 16 ways.
• A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.
• External cache support by asserting the global signal (GBL) when predefined memory banks are
accessed.
• Programmable interrupt controller (PIC).
• Local interrupt controller (LIC).
• M2 memory (shared memory):
—A 476 KB memory working at the core frequency.
—Accessible from the local bus.
—Accessible from all four SC140 cores using the MQBus.
• 4 KB bootstrap ROM.
• A QBus protocol multi-master bus connecting the four SC140 cores and the VCOP to the M2
memory.
• Data bus access of up to 128-bit read and up to 64-bit write.
• Operation at the SC140 core frequency.
• A central efficient round-robin arbiter controlling SC140 core access on the MQBus.
• Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.
SC140 Core
Extended Core
Multi-Core Shared
Memories
M2-Accessible
Multi-Core Bus
(MQBus)
Table 2.
Phase-Lock Loop (PLL)
Feature
Internal PLL
Description
• Generates up to 500 MHz core clock and up to 166 MHz bus clocks for the 60x-compatible local and
system buses and other modules.
• PLL values are determined at reset based on configuration signal values.
MSC8126 Technical Data, Rev. 11
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Freescale Semiconductor
Features
Table 3.
Buses and Memory Controller
Feature
•
•
•
•
•
Description
64/32-bit data and 32-bit address 60x bus.
Support for multiple-master designs.
Four-beat burst transfers (eight-beat in 32-bit wide mode).
Port size of 64, 32, 16, and 8 controlled by the internal memory controller.
Bus can access external memory expansion or off-device peripherals, or it can enable an external
host device to access internal resources.
• Slave support, direct access by an external host to internal resources including the M1 and M2
memories.
• On-device arbitration between up to four master devices.
A 32/64-bit wide slave host interface that operates only as a slave device under the control of an
external host processor.
• 21–25 bit address, 32/64-bit data.
• Direct access by an external host to internal and external resources, including the M1 and the M2
memories as well as external devices on the system bus.
• Synchronous and asynchronous accesses, with burst capability in the synchronous mode.
• Dual or single-strobe modes.
• Write and read buffers improve host bandwidth.
• Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.
• Sliding window mode enables access with reduced number of address pins.
• Chip ID decoding enables using one CS signal for multiple DSPs.
• Broadcast CS signal enables parallel write to multiple DSPs.
• Big-endian, little-endian, and munged little-endian support.
• 64-bit DSI, 32-bit system bus.
• 32-bit DSI, 64-bit system bus.
• 32-bit DSI, 32-bit system bus.
Flexible eight-bank memory controller:
• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a
page-mode SDRAM machine.
• Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash memory, and other user-
definable peripherals.
• Byte enables for either 64-bit or 32-bit bus width mode.
• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control
IPBus peripherals and internal memories. Each bank has the following features:
—32-bit address decoding with programmable mask.
—Variable block sizes (32 KB to 4 GB).
—Selectable memory controller machine.
—Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW)
odd/even parity for single accesses.
—Write-protection capability.
—Control signal generation machine selection on a per-bank basis.
—Support for internal or external masters on the system bus.
—Data buffer controls activated on a per-bank basis.
—Atomic operation.
—RMW data parity check (on system bus only).
—Extensive external memory-controller/bus-slave support.
—Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the
system bus only).
—Data pipeline to reduce data set-up time for synchronous devices.
60x-Compatible
System Bus
Direct Slave
Interface (DSI)
3-Mode Signal
Multiplexing
Memory Controller
MSC8126 Technical Data, Rev. 11
Freescale Semiconductor
v
