KS24A010/020/040
1K/2K/4K-bit
Serial EEPROM for Low Power
with software write protect
Data Sheet
OVERVIEW
The KS24A010/020/040 serial EEPROM has a 1,024/2,048/4,096-bit (128/256/512-byte) capacity, supporting the
standard I
2
C™-bus serial interface. It is fabricated using Samsung’s most advanced CMOS technology. It has
been developed for low power and low voltage applications (1.8 V to 5.5 V). Important features are a hardware-
based write protection circuit for the entire memory area and software-based write protection logic for the lower
128 bytes. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. The software-
based method is one-time programmable and permanent. Using one-page write mode, you can load up to 16
bytes of data into the EEPROM in a single write operation. Another significant feature of the KS24A010/020/040
is its support for fast mode and standard mode.
FEATURES
I
2
C-Bus Interface
•
•
Two-wire serial interface
Automatic word address increment
•
Operating Characteristics
•
Operating voltage
— 1.8 V to 5.5 V
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200
µA
at 5.5 V
— Maximum stand-by current: < 1
µA
at 5.5 V
•
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
•
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
•
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
•
8-pin DIP, SOP, and TSSOP
EEPROM
•
•
•
•
•
•
•
•
1K/2K/4K-bit (128/256/512-byte) storage area
16-byte page buffer
Typical 3 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
Software-based write protection for the lower
128-byte EEPROM
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
2-1
KS24A010/020/040 SERIAL EEPROM
DATA SHEET
SDA
Start/Stop
Logic
HV Generation
Timing Control
WP
Control Logic
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
EEPROM
Cell Array
128 x 8 bits
256 x 8 bits
512 x 8 bits
A0
A1
A2
Column Decoder
Data Register
D
OUT
and ACK
Figure 2-1. KS24A010/020/040 Block Diagram
2-2
DATA SHEET
KS24A010/020/040 SERIAL EEPROM
V
CC
WP
SCL SDA
KS24A010/020/040
A0
A1
A2
V
SS
NOTE:
The KS24A010/020/040 is available in
8-pin DIP, SOP, and TSSOP package.
Figure 2-2. Pin Assignment Diagram
Table 2-1. KS24A010/020/040 Pin Descriptions
Name
A0, A1, A2
Type
Input
Description
Input pins for device address selection. To configure a device address,
these pins should be connected to the V
CC
or V
SS
of the device.
These pins are internally pulled down to V
SS
.
Ground pin.
Bi-directional data pin for the I
2
C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor must
be connected to V
CC.
Typical values for this pull-up resistor are 4.7 kΩ
(100 kHz) and 1 kΩ (400 kHz).
Schmitt trigger input pin for serial clock input.
Input pin for hardware write protection control. If you tie this pin to V
CC,
the write function is disabled to protect previously written data in the
entire memory; if you tie it to V
SS
, the write function is enabled.
This pin is internally pulled down to V
SS
.
Single power supply.
Circuit
Type
1
V
SS
SDA
–
I/O
–
3
SCL
WP
Input
Input
2
1
V
CC
–
–
NOTE:
See the following page for diagrams of pin circuit types 1, 2, and 3.
2-3
KS24A010/020/040 SERIAL EEPROM
DATA SHEET
A0, A1,
A2, WP
SCL
Noise
Filter
Figure 2-3. Pin Circuit Type 1
Figure 2-4. Pin Circuit Type 2
SDA
Data Out
V
SS
Noise
Filter
Data In
Figure 2-5. Pin Circuit Type 3
2-4
DATA SHEET
KS24A010/020/040 SERIAL EEPROM
FUNCTION DESCRIPTION
I
2
C-BUS INTERFACE
The KS24A010/020/040 supports the I
2
C-bus serial interface data transmission protocol. The two-wire bus
consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected
to V
CC
by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight KS24A010/020 (four for
KS24A040) devices can be connected to the same I
2
C-bus as slaves (see Figure 2-6). Both the master and
slaves can operate as transmitter or receiver, but the master device determines which bus operating mode would
be active.
V
CC
V
CC
R
R
SDA
SCL
Slave 1
Bus Master
(Transmitter/
Receiver)
MCU
To V
CC
or V
SS
To V
CC
or V
SS
To V
CC
or V
SS
To V
CC
or V
SS
KS24A020
Tx/Rx
A0 A1 A2
Slave 2
KS24A020
Tx/Rx
A0 A1 A2
Slave 3
KS24A020
Tx/Rx
A0 A1 A2
Slave 8
KS24A020
Tx/Rx
A0 A1 A2
NOTE:
The A0 does not affect the device address of the KS24A040.
Figure 2-6. Typical Configuration (16 Kbits of Memory on the I
2
C-Bus)
2-5
