KS57C5116/P5116 MICROCONTROLLER
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
The KS57C5116/P5116 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The KS57P5116 is a
microcontroller which has 16-kbyte one-time-programmable EPROM but its functions are same to KS57C5116.
With its DTMF generator, 8-bit serial I/O interface, and versatile 8-bit timer/counters, the KS57C5116/P5116
offers an excellent design solution for a wide variety of telecommunication applications.
Up to 55 pins of the 64-pin SDIP or QFP package can be dedicated to I/O. Seven vectored interrupts provide
fast response to internal and external events. In addition, the KS57C5116/P5116's advanced CMOS technology
provides for low power consumption and a wide operating voltage range.
DEVELOPMENT SUPPORT
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based develop-
ment environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its
window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction
timing, and performance measurement applications.
The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and
accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard
hex files that also contain program control data for SMDS compatibility.
1–1
PRODUCT OVERVIEW
KS57C5116/P5116 MICROCONTROLLER
FEATURES SUMMARY
MEMORY
512
×
4-bit RAM
16,384
×
8-bit ROM
55 I/O PINS
Input only: 4 pins
I/O: 43 pins
N-channel open-drain I/O: 8 pins
MEMORY-MAPPED I/O STRUCTURE
Data memory bank 15
DTMF GENERATOR
16 dual-tone frequencies for tone dialing
8-BIT BASIC TIMER
4 interval timer functions
TWO 8-BIT TIMER/COUNTERS
Programmable interval timer
External event counter function
Timer/counters clock outputs to TCLO0 and
TCLO1 pins
External clock signal divider
Serial I/O interface clock generator
WATCH TIMER
Time interval generation: 0.5 s, 3.9 ms at 32.768
kHz
4 frequency outputs to the BUZ pin
8-BIT SERIAL I/O INTERFACE
8-bit transmit/receive mode
8-bit receive mode
LSB-first or MSB-first transmission selectable
BIT SEQUENTIAL CARRIER
Supports 8-bit serial data transfer in arbitrary
format
INTERRUPTS
3 external interrupt vectors
4 internal interrupt vectors
2 quasi-interrupts
POWER-DOWN MODES
Idle: Only CPU clock stops
Stop: System clock stops
OSCILLATION SOURCES
Crystal, ceramic for main system clock
Crystal oscillator for subsystem clock
Main system clock frequency: 3.579545 MHz
(typical)
Subsystem clock frequency: 32.768 kHz (typical)
CPU clock divider circuit (by 4, 8, or 64)
INSTRUCTION EXECUTION TIMES
0.67, 1.33, 10.7
µs
at 6.0 MHz
1.12, 2.23, 17.88 µs at 3.579545 MHz
122, 244, 1952 µs at 32.768 kHz
OPERATING TEMPERATURE
– 40
°
C to 85
°
C
OPERATING VOLTAGE RANGE
2.0 V to 5.5 V
PACKAGE TYPES
64 SDIP, 64 QFP
1–2
KS57C5116/P5116 MICROCONTROLLER
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU
All KS57-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address
up to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical,
and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two
cycles.
CPU REGISTERS
Program Counter
A 14-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the
PC is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not
increment the PC is the 1-byte REF instruction which references instructions stored in a look-up table in the
ROM. Whenever a
reset operation
or an interrupt occurs, bits PC13 through PC0 are set to the vector address.
Stack Pointer
An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in general-purpose
data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logic zero.
During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the
service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction
is executed.
The stack pointer can access the stack despite data memory access enable flag status. Since the reset value
of the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This
sets the first register of the stack area to data memory location 0FFH.
PROGRAM MEMORY
In its standard configuration, the 16,384
×
8-bit ROM is divided into four areas:
— 16-byte area for vector addresses
— 16-byte general-purpose area (0010–001FH)
— 96-byte instruction reference area
— 16,256-byte area for general-purpose program memory
The vector address area is used mostly during
reset
operations and interrupts. These 16 bytes can alternately
be used as general-purpose ROM.
The REF instruction references 2 x 1-byte or 2-byte instructions stored in reference area locations 0020H–
007FH. REF can also reference three-byte instructions such as JP or CALL. So that a REF instruction can
reference these instructions, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or
CALL is written to the reference area with the format TJP or TCALL instead of the normal instruction name.
Unused locations in the REF instruction look-up area can be allocated to general-purpose use.
1–3
PRODUCT OVERVIEW
KS57C5116/P5116 MICROCONTROLLER
DATA MEMORY
Overview
The 512
×
4 bit data memory has four areas:
— 32
×
4-bit working register area
— 224
×
4-bit general-purpose area in bank 0 which is also used as the stack area
— 256
×
4-bit general-purpose area in bank 1
— 128
×
4-bit area in bank 15 for memory-mapped I/O addresses
The data memory area is also organized as three memory banks — bank 0, bank 1, and bank 15. You use the
select memory bank instruction (SMB) to select one of the banks as working data memory.
Data stored in RAM locations are 1-, 4-, and 8-bit addressable. After a hardware reset, data memory
initialization values must be defined by program code.
Data Memory Addressing Modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When
the EMB flag is logic zero, only locations 00H–7FH of bank 0 and bank 15 can be accessed. When the EMB flag
is set to logic one, all three data memory banks can be accessed based on the current SMB value.
Working Registers
The RAM's working register area in data memory bank 0 is also divided into four
register
banks. Each register
bank has eight 4-bit registers. Paired 4-bit registers are 8-bit addressable.
Register A can be used as a 4-bit accumulator and double register EA as an 8-bit extended accumulator;
double registers WX, WL, and HL are used as address pointers for indirect addressing.
To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for
main programs and banks 1, 2, and 3 for interrupt service routines.
Bit Sequential Carrier
The bit sequential carrier (BSC) mapped in data memory bank 15 is a 8-bit general register that you can
manipulate using 1-, 4-, and 8-bit RAM control instructions.
Using the BSC register, addresses and bit locations can be specified sequentially using 1-bit indirect address-
ing instructions. In this way, a program can generate 8-bit data output by moving the bit location sequentially,
incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data
in the BSC.
1–4
KS57C5116/P5116 MICROCONTROLLER
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine
is completed, PSW values are restored.
IS1
C
IS0
SC2
EMB
SC1
ERB
SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit locations called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SRB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
Main system and subsystem oscillation circuits generate the internal clock signals for the CPU and peripheral
hardware. The main system clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated
clock signal. The subsystem clock requires either a crystal oscillator or an external clock source.
Bit settings in the 4-bit power control and system clock mode registers select the oscillation source, the CPU
clock, and the clock used during power-down mode. The internal system clock signal (fxx) can be divided inter-
nally to produce three CPU clock frequencies — fxx/4, fxx/8, or fxx/64.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW.
INT2/KS0–KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds
or 3.91 milliseconds at the watch timer clock frequency of 32.768 kHz. The following components support
interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
1–5
