KSZ8993M/ML
Integrated 3-Port 10/100 Managed
Switch with PHYs
Rev 1.06
General Description
The KSZ8993M, a highly integrated Layer 2
managed switch, is designed for low port count,
cost-sensitive 10/100 Mbps switch systems. It offers
an extensive feature set that includes tag/port-based
VLAN,
quality
of
service
(QoS)
priority,
management, management information base (MIB)
counters, MII/SNI, and CPU control/data interfaces
to effectively address both current and emerging
Fast Ethernet applications.
The KSZ8993M contains two 10/100 transceivers
with patented mixed-signal low-power technology,
three media access control (MAC) units, a high-
speed non-blocking switch fabric, a dedicated
address lookup engine, and an on-chip frame buffer
memory.
Both PHY units support 10BASE-T and 100BASE-
TX. In addition, one of the PHY unit supports
100BASE-FX.
The KSZ8993ML is the single supply version with all
the identical rich features of the KSZ8993M.
___________________________________________________________________________________________________
Functional Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2008
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Micrel, Inc.
KSZ8993M/ML
1KLook-Up
Engine
AUTO
MDI/MDI-X
10/100
T/TX/FX
PHY 1
10/100
MAC1
Queue
Manageme
nt
FIF
O,Flow Control, VLANTagging,Priority
AUTO
MDI/MDI-X
10/100
T/TX
PHY 2
10/100
MAC2
Buffer
Manageme
nt
MII/SNI
10/100
MAC3
Frame
Buffers
SNI
SPI
SPI
MIB
Counters
MIIM
SMI
I2C
P1 LED[3:0]
P2 LED[3:0]
Control
Registers
EEP
ROM
Interface
LED
Drivers
Strap-In
Configuration Pins
Features
•
Proven Integrated 3-Port 10/100 Ethernet Switch
– 2nd generation switch with three MACs and two
PHYs fully compliant to IEEE 802.3u standard
– Non-blocking switch fabric assures fast packet
delivery by utilizing a 1K MAC address lookup table
and a store-and-forward architecture
– Full duplex IEEE 802.3x flow control (pause) with
force mode option
– Half-duplex back pressure flow control
– Automatic MDI/MDI-X crossover with disable and
enable option
– 100BASE-FX support on port 1
– MII interface supports both MAC mode and PHY
mode
– 7-wire serial network interface (SNI) support for
legacy MAC
– Comprehensive LED Indicator support for link,
activity, full/half duplex and 10/100 speed
•
Comprehensive Configuration Register Access
– Serial management interface (SMI) to all internal
registers
– MII management (MIIM) interface to PHY registers
– SPI and I
2
C Interface to all internal registers
– I/0 Pins strapping and EEPROM to program
selective registers in unmanaged switch mode
– Control registers configurable on the fly (port-
priority, 802.1p/d/q, AN…)
•
QoS/CoS Packet Prioritization Support
– Per port, 802.1p and DiffServ-based
– Re-mapping of 802.1p priority field per port basis
•
Advanced Switch Features
– IEEE 802.1q VLAN support for up to 16 groups
(full-range of VLAN ID)
– VLAN ID tag/untag options, per port basis
– IEEE 802.1p/q tag insertion or removal on a per
port basis (egress)
– Programmable rate limiting from 0Mbps to
100Mbps at the ingress and egress port, rate options
for high and low priority per port basis
– Broadcast storm protection with % control (global
and per port basis)
– IEEE 802.1d spanning tree protocol support
– Upstream special tagging mode to inform the
processor which ingress port receives the packet
– IGMP v1/v2 snooping support for multicast packet
filtering
– Double-tagging support
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KSZ8993M/ML
•
Switch Management Features
– Port mirroring/monitoring/sniffing: ingress and/or
egress traffic to any port or MII
– MIB counters for fully compliant statistics
gathering, 34 MIB counters per port
– Loopback modes for remote diagnostic of failure
•
Low Power Dissipation:
<0.8 Watts (includes PHY
transmit drivers)
– Full-chip hardware power-down (register
configuration not saved)
– Per port based software power-save on PHY (idle
link detection, register configuration preserved)
– 0.18um CMOS technology
– Voltages: Core 1.8V
I/O and Transceiver 3.3V
Use K8993ML for 3.3V only operation
• Available in128-Pin PQFP
Applications
•
Universal Solutions
– Broadband gateway / Firewall / VPN
– Integrated DSL or cable modem multi-port router
– Wireless LAN access point + gateway
– Residential and enterprise VoIP gateway/phone
– Set-top/game box
– Home networking expansion
– Standalone 10/100 switch
– FTTx customer premises equipment
– Fiber broadband gateway
•
Upgradeable Solutions
(1)
– Unmanaged switch with future option to migrate to
a managed solution
– Single PHY alternative with future expansion
option for two ports
•
Industrial Solutions
– Applications requiring port redundancy and port
monitoring
– Sensor devices in redundant ring topology
Note:
1. The cost and time of PCB re-spin.
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KSZ8993M/ML
Ordering Information
Part Number
Pb-Free
KSZ8993M
KSZ8993ML
KSZ8993MI
KSZ8993MLI
Standard
KS8993M
KS8993ML
KS8993MI
KS8993MLI
Temperature Range
0
o
C to 70
o
C
0 C to 70 C
–40 C to +85 C
–40
o
C to +85
o
C
o
o
o
o
Package
128-Pin PQFP, Lead-free
128-Pin PQFP, Lead-free
128-Pin PQFP, Lead-free
128-Pin PQFP, Lead-free
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KSZ8993M/ML
Revision History
Revision
1.00
1.01
1.02
Date
5/14/03
5/28/03
12/8/03
Summary of Changes
Created.
Added KS8993MI availability in Q4 2003.
Changed V
DDIO
, V
DDATX
and V
DDARX
supply voltages
from 3.3V to (3.3V or 2.5V).
Changed [PS1,PS0] = [1,1] setting from Reserved to SMI mode.
Changed Special Tagging Mode to Upstream Special Tagging Mode
(Switch port 3 to processor support only).
Updated recommended magnetic manufacturer list.
Added 25MHz crystal/oscillator clock’s ppm spec. in Pin Description.
2
Updated I C Slave Serial Bus Configuration section.
Updated KSZ8993MI availability to from Q1 2004.
Added KS8993ML to General Description (page 1) and to the Functional
Description.
Updated Part Ordering Information table.
Updated pin description for pin 22 to the following:
V
DDC
: For KS8993M, this is an input power pin for the 1.8V digital
core V
DD
.
V
OUT
_1V8: For KS8993ML, this is an 1.8V output power pin to
supply the KS8993ML’s input power pins: V
DDAP
(pin 63), V
DDC
(pins 91, 123), and V
DDA
(pins 38,
43, 57).
Updated pin description for P1LED3 (pin 25) to indicate that an external
1K pull-down is needed if a LED is connected.
Updated pin description for MDIO (pin 95) to indicate that an external
4.7K pull-up is needed if this pin is in used.
Changed the aging period from 300 +/–75 seconds to about 200 seconds.
Updated Electrical Characteristics (V
IH
, V
IL
, V
OH
, V
OL
).
Transferred to new format.
Removed references to 2.5V operation
Added reset circuit recommendation
Updated to add Pb-Free spwcifications
Add the P/N KSZ8993I into the Ordering information table
Add the P/N KSZ8993MLI into the Ordering information table
Modify the current consumption table from board to device.
1.03
9/22/04
1.04
1.05
1.06
1.06a
4/12/05
2/14/05
2/13/07
10/28/08
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