Memory Module Specifications
KVR18R13D8/8
8GB 2Rx8 1G x 72-Bit PC3-14900
CL13 Registered w/Parity 240-Pin DIMM
DESCRIPTION
This document describes ValueRAM's 1G x 72-bit (8GB) DDR3-
1866 CL13 SDRAM (Synchronous DRAM), registered w/parity,
2Rx8 ECC memory module, based on eighteen 512M x 8-bit
FBGA components. The SPD is programmed to JEDEC stan-
dard latency DDR3-1866 timing of 13-13-13 at 1.5V. This 240-
pin DIMM uses gold contact fingers. The electrical and me-
chanical specifications are as follows:
SPECIFICATIONS
CL(IDD)
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command Time (tRFCmin)
Row Active Time (tRASmin)
Maximum Operating Power
UL Rating
Operating Temperature
Storage Temperature
13 cycles
47.125ns (min.)
260ns (min.)
34ns (min.)
3.873 W*
94 V - 0
0
o
C to 85
o
C
-55
o
C to +100
o
C
FEATURES
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JEDEC standard 1.5V (1.425V ~1.575V) Power Supply
VDDQ = 1.5V (1.425V ~ 1.575V)
933MHz fCK for 1866Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 13, 11, 10, 9, 8, 7, 6
Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
On-DIMM thermal sensor (Grade B)
Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°C
Asynchronous Reset
PCB : Height 1.180” (30.00mm), double sided component
*Power will vary depending on the SDRAM and
Register/PLL used.
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Continued >>
Document No. VALUERAM1433-001.B00
10/08/14
Page 1
MODULE DIMENSIONS:
Document No. VALUERAM1433-001.B00
Page 2
