Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
FEATURES
TI OMAP-L138 Dual Core Application
Processor
-
456 MHz (Max) C674x VLIW DSP
Floating Point DSP
32 KB L1 Program Cache
32 KB L1 Data Cache
256 KB L2 cache
1024 KB boot ROM
JTAG Emulation/Debug
456 MHz (Max) ARM926EJ-S MPU
16 KB L1 Program Cache
16 KB L1 Data Cache
8 KB Internal RAM
64 KB boot ROM
JTAG Emulation/Debug
MityDSP
MityDSP-L138F Processor Card
29-AUG-2013
-
(actual size)
APPLICATIONS
Embedded Instrumentation
Industrial Automation
Industrial Instrumentation
Medical Instrumentation
Embedded Control Processing
Network Enabled Data Acquisition
Test and Measurement
Software Defined Radio
Bar Code Scanners
Power Protection Systems
Portable Data Terminals
BENEFITS
Rapid Development / Deployment
Multiple Connectivity and Interface Options
Rich User Interfaces
High System Integration
Fixed & Floating Point Operations in Single
CPU
High Level OS Support
-
Linux
-
QNX 6.4
-
Windows Embedded CE Ready
-
ThreadX Real Time OS
Embedded Digital Signal Processing
On-Board Xilinx Spartan-6 FPGA
-
Up To XC6SLX45
Up To 2,088 KBits Block RAM
Up To 6,822 Slices (6 Input LUTs)
-
1050 Mbps data rate
-
JTAG Interface/Debug
Up To 256 MB mDDR2 CPU RAM
Up To 512 MB Parallel NAND FLASH
8 MB SPI based NOR FLASH
Integrated Power Management
Standard SO-DIMM-200 Interface
-
96 FPGA User I/O Pins
-
10/100 EMAC MII / MDIO
-
2 UARTS
-
2 McBSPs
-
2 USB Ports
-
Video Output
-
Camera/Video Input
-
MMC/SD
-
SATA
-
Single 3.3V Power Supply
DESCRIPTION
The MityDSP-L138F is a highly configurable, very small form-factor processor card that
features a Texas Instruments OMAP-L138 456 MHz (max) Applications Processor
(OMAP) tightly integrated with the Xilinx Spartan-6 Field Programmable Gate Array
(FPGA), FLASH (NAND, and NOR) and mDDR2 RAM memory subsystems. The
design of the MityDSP-L138F allows end users the capability to develop programs/logic
images for both the OMAP and the FGPA. The MityDSP-L138F provides a complete
and flexible digital processing infrastructure necessary for the most demanding embedded
applications development.
1
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP
MityDSP-L138F Processor Card
29-AUG-2013
The onboard OMAP-L138 processor provides a dual CPU core topology. The OMAP-
L138 includes an ARM926EJ-S micro-processor unit (MPU) capable of running the rich
software applications programmer interfaces (APIs) expected by modern system
designers. The ARM architecture supports several operating systems, including Linux
and Windows Embedded CE. In addition to the ARM core, the OMAP-L138 also
includes a TMS320C674x floating point digital signal processing (DSP) core. The DSP
core supports the freely provided TI DSP/BIOS real-time kernel. Users can leverage the
DSP to execute real-time compute algorithms (codecs, image/data processing,
compression techniques, filtering, etc.)
Up To 256MB
mDDR Memory
16-bit wide
8MB NOR Flash
(SPI interface)
For uBoot
bootloader
Up To 512MB
NAND Flash
8-bit wide
For root FFS
1.2V
1.8V
2.5V
3.3V
Power
Management
System
Clocks
JTAG/Emulator
EMIFA (16-bit)
JTAG
Emulator
Header
MMCSD 1
EMAC RMII
UHPI
uPP
LCD
JTAG
Header
Texas Instruments
OMAP-L138
456-MHz ARM926EJ-S ™ RISC MPU
456-MHz C674x VLIW DSP
(Many pins are multiplexed between peripherals)
Xilinx
Spartan-6
FPGA
Up To XC6SLX45
CSG324 pkg.
Programmable I/O
VPIF I/O
Programmable I/O
EMAC MII/MDIO
I/O Bank Power
Resets & RTC
UART 0,1,2
McBSP 0,1
MMCSD 0
eHRPWM
USB 0,1
McASP
SPI 0,1
I2C 0,1
Timers
eCAP
SATA
Boot Config
FPGA I/O
Banks can be
1.8V, 2.5V, or
3.3V
I/O Bank Power
Boot
Config
SO-DIMM-200 (DDR2 Connector)
Figure 1 MityDSP-L138F Block Diagram
Figure 1 provides a top level block diagram of the MityDSP-L138F processor card. As
shown in the figure, the primary interface to the MityDSP-L138F is through a standard
SO-DIMM-200 card edge interface. The interface provides power, synchronous serial
connectivity, and up to 96 pins of configurable FPGA I/O for application defined
interfacing. Details of the SO-DIMM-200 connector interface are included in the SO-
DIMM-200 Interface Description, as shown below.
2
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
3.3 V
GND
Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP
MityDSP-L138F Processor Card
29-AUG-2013
FPGA Bank I/O
The MityDSP-L138F provides 96 lines of FPGA I/O directly to the SO-DIMM-200 card
edge interface. The 96 lines of FPGA I/O are distributed across 2 banks of the FPGA.
These I/O lines and their associated logic are completely configurable within the FPGA
at the end user’s discretion.
With the Xilinx Spartan-6 series FPGA, up to the XC6SLX45, each of the user controlled
banks may be configured to operate on a different electrical interface standard based on
input voltage provided at the card edge connector. The banks support 3.3V, 2.5V, and
1.8V standard CMOS switching level technology. In addition, the I/O lines from the
FPGA have been routed as differential pairs and support higher speed LVDS standards as
well as SSTL 2.5 switching standards. Various forms of termination (pull-up/pull-down,
digitally controlled impedance matching) are available within the FPGA switch fabric.
Refer to the Xilinx Spartan 6 user’s guide for more information.
OMAP-L138 mDDR2 Memory Interface
The OMAP-L138 includes a dedicated DDR2 SDRAM memory interface shared between
the onboard ARM and DSP cores. The MityDSP-L138F includes up to 256 MB of
mDDR2 RAM integrated with the OMAP-L138 processor. The bus interface is capable
of burst transfer rates of 600 MB / second. Note that the OSCIN frequency to the OMAP-
L138 processor on the module is 24MHz.
OMAP-L138 SPI NOR FLASH Interface
The MityDSP-L138F includes 8 MB of SPI NOR FLASH. This FLASH memory is
intended to store a factory provided bootloader, and typically a compressed image of a
Linux kernel for the ARM core processor.
EMIFA - FPGA / NAND FLASH Interface
The OMAP-L138 and the Spartan-6 FPGA are connected using the DSP Asynchronous
External Memory Interface (EMIFA). The EMIFA interface includes 3 chip select
spaces. The EMIF interface supports multiple data width transfers and bus wait state
configurations based on chip select space. 8, and 16 bit data word sizes may be used.
Two of the three chip select lines (CE2, CE3) are reserved for the FPGA interface. The
MityDSP-L138F also includes 4 lines between the FPGA and the OMAP for the purposes
of generating interrupt signals.
In addition to the FPGA, up to 512 MB of on-board NAND FLASH memory is
connected to the OMAP-L138 using the EMIFA bus. The FLASH memory is 8 bits wide
and is connected to third chip select line of the EMIFA (CE1). The FLASH memory is
typically used to store the following types of data:
-
-
-
-
ARM Linux / Windows Embedded CE / QNX embedded root file-system
FPGA application images
runtime DSP or ARM software
runtime application data (non-volatile storage)
3
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP
MityDSP-L138F Processor Card
29-AUG-2013
OMAP-L138 Camera and Video Interfaces
The OMAP-L138 includes an optional video port I/O interface commonly used to drive
LCD screens as well as a camera input interface. These interfaces have been routed to
the FPGA, which may be routed to the FPGA output pins on the SO-DIMM-200
connector. By routing the video data through the FPGA, additional user customization
and/or processing (e.g., overlays of video output, preprocessing or filtering of camera
input) may be offloaded from the OMAP-L138 to the FPGA for computation intensive
applications.
Debug Interface
Both the JTAG interface signals for the FPGA and the JTAG and emulator signals for the
OMAP-L138 processor have been brought out to a Hirose header that is intended for use
with an available Critical Link breakout adapter. This header can be removed for
production units; please contact your Critical Link representative for details.
This adapter is not included with individual modules but is included with each Critical
Link Development Kit that is ordered. If an adapter, Critical Link (CL) part number
80-000286, is needed please contact your Critical Link representative.
Software and Application Development Support
Users of the MityDSP-L138F are encouraged to develop applications and FPGA
firmware using the MityDSP-L138F hardware and software development kit provided by
Critical Link LLC.
The development kit includes an implementation of an
OpenEmbedded board support package providing an Angstrom based Linux distribution
and compatible gcc compiler tool-chain with debugger. In addition, the development kit
includes support libraries necessary to program the DSP core using the TI Code
Composer Studio DSP compiler tool-chain.
To support rapid FPGA and applications development, netlist components - compatible
with the Xilinx ISE FPGA synthesis tool – for commonly used FPGA designs and a
corresponding set of Linux loadable kernel modules and/or DSP interface APIs are
included.
The libraries provide the necessary functions needed to configure the
MityDSP-L138F, program standalone embedded applications, and interface with the
various hardware components both on the processor board as well as a custom
application carrier card. The libraries include several interface “cores” – FPGA and DSP
software modules designed to interface with various high performance data converter
modules (ADCs, DACs, LCD and touchscreen interfaces, etc) – as well as bootloading
and FLASH programming utilities.
Growth Options
The OMAP-L138 has been designed to support several upgrade options. These options
include various speed grades, memory configurations, and operating temperature
specifications including commercial and industrial temperature ranges. The available
options are listed in the section below containing ordering information. For additional
ordering information and details regarding these options, or to inquire about a particular
configuration not listed below, please contact a Critical Link sales representative.
4
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP
MityDSP-L138F Processor Card
29-AUG-2013
ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified cards are
required, please contact the Critical Link Sales
Office or unit Distributors for availability and
specifications.
Maximum Supply Voltage, Vcc
Storage Temperature Range
Shock, Z-Axis
Shock, X/Y-Axis
3.5 V
-65
o
C to 80
o
C
±10 g
±10 g
OPERATING CONDITIONS
Ambient Temperature
Range Commercial
Ambient Temperature
Range Industrial
Humidity
MIL-STD-810F
0
o
C to 70
o
C
-40
o
C to 85
o
C
0 to 95%
Non-condensing
Contact Critical
Link for Details
SO-DIMM-200 Interface Description
The primary interface connector for the MityDSP-L138 is the SO-DIMM card edge
interface which contains 4 types of signals:
Power (PWR)
Dedicated signals mapped to the OMAP-L138 device (D)
Multi-function signals mapped to the OMAP-L138 device (M)
Dedicated signals mapped to the Xilinx Spartan 6 device (F)
Table 1 contains a summary of the MityDSP-L138 pin mapping.
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Ball
-
-
-
-
-
K14
J1
J2
L1
L2
P16
P18
P19
N19
M18
M19
K18
-
-
-
Type
PWR
PWR
PWR
PWR
PWR
D
D
D
D
D
D
D
D
D
D
D
D
D
PWR
PWR
I/O
-
-
-
-
-
I
O
O
I
I
I
I/O
I/O
O
I/O
I/O
O
-
-
-
Table 1 SO-DIMM Pin-Out
Signal
Pin Ball Type
+3.3 V in
2
-
PWR
+3.3 V in
4
-
PWR
+3.3 V in
6
-
PWR
GND
8
-
PWR
GND
10
-
PWR
RESET_IN#
12
-
D
SATA_TX_P
14
A4
M
SATA_TX_N
16
A3
M
SATA_RX_P
18
A2
M
SATA_RX_N
20
A1
M
USB0_ID
22
B4
M
USB1_D_N
24
B1
M
USB1_D_P
26
B2
M
USB0_VBUS
28
B3
M
USB0_D_N
30
C2
M
USB0_D_P
32
C3
M
USB0_DRVVBUS
34
C4
M
3V RTC Battery
36
C5
M
+3.3 V in
38
-
PWR
+3.3 V in
40
-
PWR
I/O
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
Signal
+3.3 V in
+3.3 V in
+3.3 V in
GND
GND
EXT_BOOT#
GP0_7
GP0_10
GP0_11
GP0_15
GP0_6
GP0_14
GP0_12
GP0_5
GP0_13
GP0_1
GP0_4
GP0_3
+3.3 V in
+3.3 V in
5
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
