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LA4064C-75TN128E

EE PLD, 8 ns, PQFP100
电子可编程逻辑器件, 8 ns, PQFP100

器件类别:半导体    可编程逻辑器件   

厂商名称:Lattice(莱迪斯)

厂商官网:http://www.latticesemi.com

下载文档
器件参数
参数名称
属性值
功能数量
1
端子数量
100
最大工作温度
125 Cel
最小工作温度
-40 Cel
最大供电/工作电压
3.6 V
最小供电/工作电压
3 V
额定供电电压
3.3 V
输入输出总线数量
64
加工封装描述
LEAD FREE, TQFP-100
无铅
Yes
欧盟RoHS规范
Yes
中国RoHS规范
Yes
状态
ACTIVE
工艺
CMOS
包装形状
SQUARE
包装尺寸
FLATPACK, LOW PROFILE, FINE PITCH
表面贴装
Yes
端子形式
GULL WING
端子间距
0.5000 mm
端子涂层
MATTE TIN
端子位置
QUAD
包装材料
PLASTIC/EPOXY
温度等级
AUTOMOTIVE
组织
0 DEDICATED INPUTS, 64 I/O
最大FCLK时钟频率
168 MHz
输出功能
MACROCELL
可编程逻辑类型
EE PLD
传播延迟TPD
8 ns
专用输入数量
0.0
文档预览
LA-ispMACH 4000V/Z
Automotive Family
3.3V/1.8V In-System Programmable
SuperFAST
TM
High Density PLDs
May 2009
Data Sheet DS1017
Features
High Performance
• f
MAX
= 168MHz maximum operating frequency
• t
PD
= 7.5ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-Fit
TM
and refit
• Fast path, SpeedLocking
TM
Path, and wide-PT
path
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable
(ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free (RoHS) package
Introduction
The high performance LA-ispMACH 4000V/Z automo-
tive family from Lattice offers a SuperFAST CPLD solu-
tion that is tested and qualified to the AEC-Q100
standard. The family is a blend of Lattice’s two most
popular architectures: the ispLSI
®
2000 and ispMACH
4A. Retaining the best of both families, the LA-ispMACH
4000V/Z architecture focuses on significant innovations
to combine the highest performance with low power in a
flexible CPLD family.
The LA-ispMACH 4000V/Z automotive family combines
high speed and low power with the flexibility needed for
ease of design. With its robust Global Routing Pool and
Output Routing Pool, this family delivers excellent First-
Time-Fit, timing predictability, routing, pin-out retention
and density migration.
Zero Power (LA-ispMACH 4000Z)
• Typical static current 10µA (4032Z)
• 1.8V core low dynamic power
• LA-ispMACH 4000Z operational down to 1.6V
AEC-Q100 Tested and Qualified
• Automotive: -40 to 125°C ambient (T
A
)
Easy System Integration
• Superior solution for power sensitive consumer
applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V) or 1.8V (4000Z)
supplies
Table 1. LA-ispMACH 4000V Automotive Family Selection Guide
LA-ispMACH 4032V
Macrocells
I/O + Dedicated Inputs
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltage (V)
Pins/Package
32
30+2/32+4
7.5
4.5
4.5
168
3.3V
44-pin Lead-Free TQFP
48-pin Lead-Free TQFP
LA-ispMACH 4064V
64
30+2/32+4/64+10
7.5
4.5
4.5
168
3.3V
44-pin Lead-Free TQFP
48-pin Lead-Free TQFP
100-pin Lead-Free TQFP
LA-ispMACH 4128V
128
64+10/92+4/96+4
7.5
4.5
4.5
168
3.3V
100-pin Lead-Free TQFP
128-pin Lead-Free TQFP
144-pin Lead-Free TQFP
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1017_02.5
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Table 2. LA-ispMACH 4000Z Automotive Family Selection Guide
LA-ispMACH 4032Z
Macrocells
I/O + Dedicated Inputs
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltage (V)
Pins/Package
32
32+4
7.5
4.5
4.5
168
1.8V
48-pin Lead-Free TQFP
LA-ispMACH 4064Z
64
32+4/64+10
7.5
4.5
4.5
168
1.8V
48-pin Lead-Free TQFP
100-pin Lead-Free TQFP
LA-ispMACH 4128Z
128
64+10
7.5
4.5
4.5
168
1.8V
100-pin Lead-Free TQFP
The LA-ispMACH 4000V/Z automotive family offers densities ranging from 32 to 128 macrocells. There are multiple
density-I/O combinations in Thin Quad Flat Pack (TQFP) packages ranging from 44 to 144 pins. Tables 1 and 2
show the macrocell, package and I/O options, along with other key parameters.
The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3V (4000V
and 1.8V (4000Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LA-
ispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper
latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LA-ispMACH 4000V/Z
automotive family is in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1
boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface sig-
nals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The LA-ispMACH 4000V/Z automotive devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks
(GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O
Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1.
Figure 1. Functional Block Diagram
CLK0/I
CLK1/I
CLK2/I
CLK3/I
V
CCO0
GND
V
CCO1
GND
I/O
Block
ORP
I/O Bank 1
16
36
Generic
16
Logic
Block
I/O
Block
ORP
GOE0
GOE1
V
CC
GND
TCK
TMS
TDI
TDO
I/O
Block
ORP
I/O Bank 0
16
Global Routing Pool
Generic
Logic
Block
16
36
16
36
Generic
16
Logic
Block
I/O
Block
ORP
16
Generic
Logic
Block
16
36
2
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
The I/Os in the LA-ispMACH 4000V/Z automotive devices are split into two banks. Each bank has a separate I/O
power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs
support the standards compatible with the power supply provided to the bank. Support for a variety of standards
helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified
within an I/O bank that is connected to V
CCO
of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
LA-ispMACH 4000V/Z Automotive Architecture
There are a total of two GLBs in the LA-ispMACH 4032V/Z, increasing to 8 GLBs in the LA-ispMACH 4128V/Z.
Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into
the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same
GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with
consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them
to the associated I/O cells in the I/O block.
Generic Logic Block
The LA-ispMACH 4000V/Z Automotive GLB consists of a programmable AND array, logic allocator, 16 macrocells
and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O
pins are decoupled from macrocells through the ORP. Figure 2 illustrates the GLB.
Figure 2. Generic Logic Block
CLK0
CLK1
CLK2
CLK3
To GRP
Clock
Generator
1+OE
16 MC Feedback Signals
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
To ORP
To
Product Term
Output Enable
Sharing
Logic Allocator
36 Inputs
from GRP
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
AND Array
36 Inputs,
83 Product Terms
3
16 Macrocells
Lattice Semiconductor
Figure 3. AND Array
In[0]
In[34]
In[35]
LA-ispMACH 4000V/Z Automotive Family Data Sheet
PT0
PT1
PT2
PT3
PT4
Cluster 0
PT75
PT76
PT77
Cluster 15
PT78
PT79
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE
Note:
Indicates programmable fuse.
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the LA-ispMACH 4000V/Z automotive family is 4+1 (total
5) product terms. The software automatically considers the availability and distribution of product term clusters as it
fits the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path,
20-PT Speed Locking path and an up to 80-PT path. The availability of these three paths lets designers trade tim-
ing variability for increased performance.
The enhanced Logic Allocator of the LA-ispMACH 4000V/Z automotive family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
to to
n-1 n-2
from from
n-1 n-4
Fast 5-PT
Path
1-80
PTs
To XOR (MC)
From
n-4
n
5-PT
Cluster
to
n+1
Individual Product
Term Allocator
from
n+2
Cluster
Allocator
from
n+1
To
n+4
SuperWIDE™
Steering Logic
4
Lattice Semiconductor
Product Term Allocator
LA-ispMACH 4000V/Z Automotive Family Data Sheet
The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-
ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate
output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic
allocator.
Table 3. Individual PT Steering
Product Term
PT
n
PT
n
+1
PT
n
+2
PT
n
+3
PT
n
+4
Logic
Logic PT
Logic PT
Logic PT
Logic PT
Logic PT
Single PT for XOR/OR
Individual Clock (PT Clock)
Individual Initialization or Individual Clock Enable (PT Initialization/CE)
Individual Initialization (PT Initialization)
Individual OE (PTOE)
Control
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.
Table 4. Available Clusters for Each Macrocell
Macrocell
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
Available Clusters
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-
tor
n
+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term
chains.
5
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