Ordering number ::ENA2011A
Ordering number ENA2011A
LA4425PV
Monolithic Linear IC
5W Power Amplifier
with Very Few External Parts
for Car Radio and Car Stereo
Overview
http://onsemi.com
The LA4425PV is a 5W power amplifier with very few external parts. Encapsulated in a surface mount package
[SSOP44K (275 mil)], it is designed for operation without a heat sink. Only two external parts (Only IN/OUT coupling
capacitors). Almost no evaluation, adjustment and check of its functions as a power IC required, enabling control to be
simplified and set patterns to be further miniaturized.
Functions
•
Wide operation supply range
→
5 to 16V
•
On-chip protection:
- Over-voltage protection
- Thermal protection
- Output D.C. short protection .
•
On-chip pop noise reducing circuit
Specifications
Maximum Ratings
at Ta = 25°C
Parameter
Maximum supply voltage
Surge maximum supply voltage
Maximum output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VCC max
VCC surge
IO peak
Pd max
Topr
Tstg
When mounted on the specified PCB
Rg = 0Ω
Giant pulse 200ms
Rise time 1ms
3.3
5.15
-40 to +85
-40 to +150
A
W
°C
°C
Conditions
Ratings
18
50
Unit
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
June, 2013
31412 SY/22912 SY 20110916 S00002 No.A2011-1/8
LA4425PV
Operating Conditions
at Ta = 25°C,
Parameter
Recommended supply voltage
Recommended load resistance
Operating voltage range
Operating load resistance range
Symbol
VCC
RL
VCC op
RL op
Under conditions where maximum ratings are
not exceeded
Conditions
Ratings
13.2
4
5 to 16
2 to 8
Unit
V
Ω
V
Ω
Electrical Characteristics
at Ta
=
25°C, VCC = 13.2V, RL = 4Ω, f = 1 kHz, Rg = 600Ω, Specified board/specified circuit
Ratings
Parameter
Quiescent current
Voltage gain
Output power
Symbol
ICCO
VG
PO1
PO2
Total harmonic distortion
Output noise voltage
Ripple rejection ratio
THD
VNO
SVRR1
VO = 0dBm
13.2 V / 4Ω, THD = 10%
14.4 V / 4Ω, THD = 10%
VO = 2Vrms
Rg = 0Ω, BPF = 20 Hz to 20 kHz
Rg = 0Ω, BPF = 20 Hz to 20 kHz
VR = 0dBm, fR = 100Hz
SVRR2
Rg = 0Ω, BPF = 20 Hz to 20 kHz
VR = 0dBm, fR = 1kHz
Over-voltage attack
Starting time
Input resistance
Roll-off frequency
VCCX
tS
RIN
fL
fH
Rg = 0Ω
21.5
0.35
50
40
90
V
s
kΩ
Hz
kHz
47
dB
30
43
4
5
Conditions
min
typ
65
45
5
6
0.1
0.15
40
1.0
0.5
max
130
47
mA
dB
W
W
%
mV
dB
Unit
Package Dimensions
unit : mm (typ)
3333
TOP VIEW
15.0
44
23
SIDE VIEW
BOTTOM VIEW
(4.7)
5.6
7.6
(3.5)
1
(0.68)
0.65
0.22
22
0.2
1.7MAX
SIDE VIEW
0.1 (1.5)
0.5
SANYO : SSOP44K(275mil)
No.A2011-2/8
LA4425PV
6.0
Pd max -- Ta
5.15
Maximum power dissipation, Pd max -- W
5.0
4.0
3.0
2.68
2.0
Board specifications of the Pdmax - Ta measurement
(LA4425PV specified PCB)
Size: 70mm
×
70mm
×
1.6mm
3
(Four layer boards)
Copper foil thickness: L1/L4=18µm, L2/L3=35µm
Materials: FR-4 (Glass cloth matrix epoxy resin)
1.0
0
-40
-20
0
20
40
60
80
100
Ambient temperature, Ta -- C
L1: Figure of copper wiring pattern
L2: Figure of copper wiring pattern
L3: Figure of copper wiring pattern
L4: Figure of copper wiring pattern
Notes:
The data for the case with the exposed die-pad substrate mounted shows the values when 95% or more of the Exposed
Die-Pad is wet.
1. For the set design, employ the derating design with sufficient margin.
2. Stresses to be derated include the voltage, current, junction temperature, power loss, and mechanical stresses such
as vibration, impact, and tension.
Accordingly, the design must ensure these stresses to be as low or small as possible.
The guideline for ordinary derating is shown below:
(1) Maximum value 80% or less for the voltage ratings
(2) Maximum value 80% or less for the current ratings
(3) Maximum value 80% or less for the temperature ratings
3. After the set has been designed, be sure to verify the design with the actual product. Confirm the solder joint state
and verify also the reliability of solder joint for the Exposed Die-Pad, etc. Any void or deterioration, if observed in
the solder joint of these parts, causes deteriorated thermal conduction, possibly resulting in thermal destruction of
IC.
No.A2011-3/8
LA4425PV
Pin Assignment
POWERGND
POWERGND
OUT
VCC
VCC
OUT
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
LV4425PV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
IN
•
Connect exposed die pad on the back side to GND with a large pattern.
•
Pins whose names are not given next to the pin numbers are all “NC pins” that are not connected to the chip inside the
package, and they must not be used as relay pins.
Application Circuit Example
VCC
IN
36 37
+
+
10
LA4425PV
14
15
33
+
34
OUT
PREGND
30 31
POWERGND
•
On-chip overvoltage protection
•
On-chip thermal protection
•
On-chip pop noise reducing circuit
•
On-chip output D.C. short protection
Pin Voltage
at VCC = 13.2V
Characteristics
Pin No.
Pin voltage
(reference value)
Input
10
(≈ 2VBE)
1.4V
Pre GND
14, 15
0V
Power GND
30, 31
0V
Output
33, 34
(≈ 1/2VCC)
6.5V
VCC
36, 37
(VCC)
13.2V
PREGND
PREGND
No.A2011-4/8
LA4425PV
IC Usage Notes
•
Maximum ratings
If the IC is used in the vicinity of the maximum ratings, even a slight variation in conditions may cause the maximum
ratings to be exceeded, thereby leading to a breakdown.
•
Printed circuit board
When drawing the printed circuit pattern, refer to the sample printed circuit pattern. Be careful not to form a feedback
loop between input and output.
Always use both pins of the Pre GND, Power GND, OUT and VCC when designing the layout.
•
Exposed Die-Pad
The exposed die pad on the back side of the IC must be connected to GND with a large pattern surface area.
•
Load Resistance and Misoperation
It should be noted that when RL
<
2Ω and VCC is high, and the switch is turned “ON” when setting is for a signal (THD
= 10%), the ground detector (current
×
voltage Schmitt circuit) operates momentarily.
•
Starting Time (ts)
This is set at 0.35sec/typ, but it can be made shorter by making input capacitor Ci smaller, or longer by making it larger.
•
Pop noise
The pop noise prevention circuit operates to reduce pop until Rg reaches 50kΩ. However, if Rg is left open, the charging
route of input capacitor Ci is lost, so the pop noise reduction circuit stops operating and click noises become louder.
•
VG/OSC
The voltage gain is fixed at 45dB inside the IC. It is impossible to change it externally.
Phase compensation capacitors (350pF/total) are connected between individual stages inside the IC, and the open loop
gain is low. In addition, the upper and lower drives are made equivalent so that final stage current gain is adjusted,
providing a measure against unwanted high-frequency parasitic oscillation peculiar to power IC’s.
•
BTL Connection
Connection is impossible with IC alone.
PS No.A2011-5/8
