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LAN9303/LAN9303i

Small Form Factor Three

Port 10/100 Managed

Ethernet Switch with Single

MII/RMII/Turbo MII

PRODUCT FEATURES

Highlights

Up to 200Mbps via Turbo MII Interface

High performance, full featured 3 port switch with

VLAN, QoS packet prioritization, Rate Limiting, IGMP

monitoring and management functions

Serial management via I

C or SMI

Unique Virtual PHY feature simplifies software

development by mimicking the multiple switch ports

as a single port PHY

Switch Management

— Port mirroring/monitoring/sniffing: ingress and/or egress

traffic on any port or port pair

— Fully compliant statistics (MIB) gathering counters

— Control registers configurable on-the-fly

Datasheet

Ports

—

Port 0 - MII MAC, MII PHY, RMII PHY modes

2 internal 10/100 PHYs with HP Auto-MDIX support

200Mbps Turbo MII (PHY or MAC mode)

Fully compliant with IEEE 802.3 standards

10BASE-T and 100BASE-TX support

Full and half duplex support

Full duplex flow control

Backpressure (forced collision) half duplex flow control

Automatic flow control based on programmable levels

Automatic 32-bit CRC generation and checking

2K Jumbo packet support

Programmable interframe gap, flow control pause value

Full transmit/receive statistics

Full LED support per port

Auto-negotiation

Automatic polarity correction

Automatic MDI/MDI-X

Loop-back mode

Target Applications

Cable, satellite, and IP set-top boxes

Digital televisions

Digital video recorders

VoIP/Video phone systems

Home gateways

Test/Measurement equipment

Industrial automation systems

Key Benefits

Ethernet Switch Fabric

— 32K buffer RAM

— 512 entry forwarding table

— Port based IEEE 802.1Q VLAN support (16 groups)

– Programmable IEEE 802.1Q tag insertion/removal

— IEEE 802.1D spanning tree protocol support

— 4 separate transmit queues available per port

— Fixed or weighted egress priority servicing

— QoS/CoS Packet prioritization

– Input priority determined by VLAN tag, DA lookup,

TOS, DIFFSERV or port default value

– Programmable Traffic Class map based on input

priority on per port basis

– Remapping of 802.1Q priority field on per port basis

– Programmable rate limiting at the ingress with

coloring and random early discard, per port / priority

– Programmable rate limiting at the egress with leaky

bucket algorithm, per port / priority

— IGMP v1/v2/v3 monitoring for Multicast packet filtering

— Programmable broadcast storm protection with global

% control and enable per port

— Programmable buffer usage limits

— Dynamic queues on internal memory

— Programmable filter by MAC address

SMSC LAN9303/LAN9303i

Serial Management

— I

C (slave) access to all internal registers

— MIIM (MDIO) access to PHY related registers

— SMI (extended MIIM) access to all internal registers

— General Purpose Timer

— I

C Serial EEPROM interface

— Programmable GPIOs/LEDs

Other Features

Single 3.3V power supply

ESD Protection Levels

— ±8kV HBM without External Protection Devices

— ±8kV contact mode (IEC61000-4-2)

— ±15kV air-gap discharge mode (IEC61000-4-2)

Latch-up exceeds ±150mA per EIA/JESD 78

56-pin QFN (8x8 mm) Lead-Free RoHS Compliant

Package

Available in Commercial & Industrial Temp. Ranges

DATASHEET

Revision 1.3 (08-27-09)

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

ORDER NUMBERS:

LAN9303-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70°C TEMP RANGE)

LAN9303i-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO 85°C TEMP RANGE)

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC

reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications

before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent

rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated

version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not

designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property

damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of

this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered

trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,

FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE

OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL

DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;

TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD

TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.3 (08-27-09)

DATASHEET

SMSC LAN9303/LAN9303i

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

Table of Contents

Chapter 1 Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.1

General Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 System Clocks/Reset/PME Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 System Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Ethernet PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.6 I2C Slave Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7 SMI Slave Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.8 EEPROM Controller/Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.9 GPIO/LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Internal PHY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 MAC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 PHY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Management Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1

Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 56-QFN Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3

Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4 Clocking, Resets, and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.1

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.1 Chip-Level Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.2

4.2.3

4.2.4

4.2.4.1

4.2.4.2

4.2.3.1

4.2.3.2

4.2.3.3

4.2.2.1

4.2.1.1

4.2.1.2

Multi-Module Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Single-Module Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Power-On Reset (POR) .................................................................................................................................................................................. 43

nRST Pin Reset .............................................................................................................................................................................................. 43

Digital Reset (DIGITAL_RST) ......................................................................................................................................................................... 44

Port 2 PHY Reset............................................................................................................................................................................................ 44

Port 1 PHY Reset............................................................................................................................................................................................ 45

Virtual PHY Reset ........................................................................................................................................................................................... 45

Soft-Straps ...................................................................................................................................................................................................... 46

Hard-Straps..................................................................................................................................................................................................... 52

Configuration Straps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.3.1 Port 1 & 2 PHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.2 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.3 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.4 General Purpose Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.5 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.6 Device Ready Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SMSC LAN9303/LAN9303i

DATASHEET

Revision 1.3 (08-27-09)

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

Chapter 6 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.1

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2

Switch Fabric CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1 Switch Fabric CSR Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.2 Switch Fabric CSR Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.3 Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3

10/100 Ethernet MACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1 Receive MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.2

6.3.2.1

6.3.1.1

Transmit MAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Receive Counters ........................................................................................................................................................................................... 65

Transmit Counters .......................................................................................................................................................................................... 66

6.4

Switch Engine (SWE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.4.1 MAC Address Lookup Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.4.1.1

6.4.1.2

6.4.1.3

6.4.1.4

6.4.1.5

6.4.1.6

6.4.1.7

6.4.2

6.4.3

6.4.3.1

6.4.3.2

6.4.3.3

6.4.3.4

Forwarding Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Transmit Priority Queue Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Learning/Aging/Migration ................................................................................................................................................................................ 68

Static Entries................................................................................................................................................................................................... 68

Multicast Pruning ............................................................................................................................................................................................ 68

Address Filtering ............................................................................................................................................................................................. 68

Spanning Tree Port State Override................................................................................................................................................................. 68

MAC Destination Address Lookup Priority...................................................................................................................................................... 68

Host Access .................................................................................................................................................................................................... 68

6.4.4

6.4.5

6.4.6

6.4.7

6.4.8

6.4.9

6.4.10

6.4.10.1

6.4.10.2

6.4.6.1

VLAN Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Spanning Tree Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Ingress Flow Metering and Coloring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Broadcast Storm Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IPv4 IGMP Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host CPU Port Special Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port Default Priority......................................................................................................................................................................................... 73

IP Precedence Based Priority ......................................................................................................................................................................... 73

DIFFSERV Based Priority............................................................................................................................................................................... 73

VLAN Priority .................................................................................................................................................................................................. 73

Ingress Flow Calculation................................................................................................................................................................................. 77

6.4.11 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.5

Buffer Manager (BM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.5.1 Packet Buffer Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.5.2 Random Early Discard (RED). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.3 Transmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.4 Transmit Priority Queue Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.5 Egress Rate Limiting (Leaky Bucket) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.6 Adding, Removing, and Changing VLAN Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.7 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6

Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.1.1

Packets from the Host CPU ............................................................................................................................................................................ 80

Packets to the Host CPU ................................................................................................................................................................................ 81

Buffer Limits and Flow Control Levels ............................................................................................................................................................ 82

Chapter 7 Ethernet PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.1

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.1 PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2

Port 1 & 2 PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1.1

7.2.1.2

7.2.1.3

7.2.1.4

7.2.1.5

7.2.1.6

7.2.2.1

7.2.2.2

7.2.2

100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

MII MAC Interface ........................................................................................................................................................................................... 90

4B/5B Encoder................................................................................................................................................................................................ 90

Scrambler and PISO ....................................................................................................................................................................................... 92

NRZI and MLT-3 Encoding ............................................................................................................................................................................. 92

100M Transmit Driver ..................................................................................................................................................................................... 92

100M Phase Lock Loop (PLL) ........................................................................................................................................................................ 92

A/D Converter ................................................................................................................................................................................................. 93

DSP: Equalizer, BLW Correction and Clock/Data Recovery .......................................................................................................................... 93

Revision 1.3 (08-27-09)

DATASHEET

SMSC LAN9303/LAN9303i

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

7.2.2.3

7.2.2.4

7.2.2.5

7.2.2.6

7.2.2.7

7.2.3.1

7.2.3.2

NRZI and MLT-3 Decoding ............................................................................................................................................................................. 94

Descrambler and SIPO ................................................................................................................................................................................... 94

5B/4B Decoding .............................................................................................................................................................................................. 94

Receiver Errors ............................................................................................................................................................................................... 94

10M TX Driver and PLL .................................................................................................................................................................................. 95

7.2.3

7.2.4

7.2.4.1

7.2.4.2

7.2.4.3

7.2.4.4

10BASE-T Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10BASE-T Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.2.5

7.2.5.1

7.2.5.2

7.2.5.3

7.2.5.4

7.2.5.5

PHY Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Filter and Squelch ........................................................................................................................................................................................... 95

10M RX and PLL............................................................................................................................................................................................. 95

Jabber Detection............................................................................................................................................................................................. 96

PHY Pause Flow Control ................................................................................................................................................................................ 97

Parallel Detection............................................................................................................................................................................................ 98

Restarting Auto-Negotiation............................................................................................................................................................................ 98

Disabling Auto-Negotiation ............................................................................................................................................................................. 98

Half Vs. Full-Duplex ........................................................................................................................................................................................ 98

7.2.6

7.2.7

7.2.8

7.2.9

7.2.9.1

7.2.9.2

7.2.8.1

HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

MII MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PHY Management Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

PHY Interrupts .............................................................................................................................................................................................. 100

PHY General Power-Down ........................................................................................................................................................................... 101

PHY Energy Detect Power-Down ................................................................................................................................................................. 101

7.2.10 PHY Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

7.2.11 LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.12 Required Ethernet Magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3

Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1 Virtual PHY Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.2

7.3.3

7.3.3.1

7.3.3.2

7.3.2.1

7.3.1.1

7.3.1.2

7.3.1.3

7.2.10.1

7.2.10.2

7.2.10.3

PHY Software Reset via RESET_CTL.......................................................................................................................................................... 101

PHY Software Reset via PHY_BASIC_CTRL_x ........................................................................................................................................... 101

PHY Power-Down Reset............................................................................................................................................................................... 101

102

Virtual PHY in MAC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Virtual PHY Pause Flow Control ................................................................................................................................................................... 104

Full-Duplex Flow Control............................................................................................................................................................................... 104

Virtual PHY Software Reset via RESET_CTL .............................................................................................................................................. 104

Virtual PHY Software Reset via VPHY_BASIC_CTRL ................................................................................................................................. 105

Virtual PHY Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Chapter 8 Serial Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8.1

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2

I2C Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3

I2C Master EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.1 I2C EEPROM Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.2 I2C EEPROM Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.3 I2C EEPROM Sequential Byte Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.4 I2C EEPROM Byte Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.5 Wait State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.6 I

C Bus Arbitration and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.6.1

8.3.6.2

8.3.6.3

8.3.6.4

106

107

108

109

110

8.3.7 I2C Master EEPROM Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4

EEPROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.1 EEPROM Loader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.2 EEPROM Valid Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.3 MAC Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.4 Soft-Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.5

8.4.4.1

8.4.4.2

8.4.4.3

Bus Busy....................................................................................................................................................................................................... 110

Clock Synchronization .................................................................................................................................................................................. 110

Arbitration...................................................................................................................................................................................................... 111

Timeout Due to Busy or Arbitration............................................................................................................................................................... 111

111

113

115

Register Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

PHY Registers Synchronization.................................................................................................................................................................... 115

Virtual PHY Registers Synchronization......................................................................................................................................................... 116

LED and Manual Flow Control Register Synchronization ............................................................................................................................. 116

SMSC LAN9303/LAN9303i

DATASHEET

Revision 1.3 (08-27-09)