* Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
90110 SY 20100827-S00001 / D1306 MS IM 20060404-S00004 No.A0606-1/12
LB11693JH
Allowable Operating Ranges
at Ta = 25°C
Parameter
Supply voltage range
Constant voltage output current
RD output current
FG output current
Symbol
VCC
IREG
IRD
IFG
Conditions
Ratings
8 to 28
0 to -30
0 to 10
0 to 10
Unit
V
mA
mA
mA
Electrical Characteristics
at Ta = 25°C, VCC = VM = 24V
Ratings
Parameter
Current drain 1
Current drain 2
[Output Block]
Output saturation voltage 1
Output saturation voltage 2
Output leakage current
High side diode forward voltage 1
High side diode forward voltage 2
[5V Constant Voltage Output]
Output voltage
Line regulation
Load regulation
[Hall Amplifier]
Input bias current
Hall sensor input sensitivity
Common-mode input voltage range
Input offset voltage
[CSD Pin]
High-level output voltage
Low-level output voltage
External capacitor charge current
External capacitor discharge current
Charge/discharge current ratio
VOH(CSD)
VOL(CSD)
ICSD1
ICSD2
RCSD
Charge current/discharge current
2.75
0.85
-3.3
0.09
3.0
1.0
-2.4
0.17
14
3.25
1.15
-1.4
0.23
V
V
μA
μA
Times
IB(HA)
VHIN
VICM
VIOH
Sine wave input
Differential input 50mVp-p
Design target value*
50
1.5
-20
2
10
350
VREG-1.0
+20
μA
mVp-p
V
mV
VREG
ΔVREG1
ΔVREG2
IO = -5mA
VCC = 9.5 to 28V
IO = -5 to -20mA
4.7
5.0
30
20
5.3
100
100
V
mV
mV
VOsat1
VOsat2
IOleak
VD1
VD2
ID = 0.7A
ID = 1.5A
1.25
1.9
IO = 0.7A,VO(SINK)+VO(SOURCE)
IO = 1.5A,VO(SINK)+VO(SOURCE)
1.5
2.2
2.05
2.9
100
1.65
2.5
V
V
μA
V
V
Symbol
ICC1
ICC2
When STOP
Conditions
min
typ
10
4.0
max
13.5
5.5
mA
mA
unit
[Undervoltage Protection Circuit (LVS Pin)]
Operating voltage
Release voltage
Hysteresis
[Current Limiter Circuit]
Limiter voltage
[Thermal Shutdown Operation]
Thermal shutdown operating
temperature
Hysteresis
[CTL Amplifier]
Input offset voltage
Input bias current
Common-mode input voltage range
High-level output voltage
Low-level output voltage
Open-loop gain
VIO(CTL)
IB(CTL)
VICM
VOH(CTL)
VOL(CTL)
G(CTL)
ITOC = -0.2mA
ITOC = 0.2mA
f(CTL) = 1kHz
45
-10
-1
0
VREG-1.2
VREG-0.8
0.8
51
1.05
10
1
VREG-1.7
mV
μA
V
V
V
dB
ΔTSD
TSD
Design target value*
(junction temperature)
Design target value*
(junction temperature)
150
170
40
°C
°C
VRF
VCC-VM
0.45
0.5
0.55
V
VSDL
VSDH
ΔVSD
3.6
4.1
0.35
3.8
4.3
0.5
4.0
4.5
0.65
V
V
V
*: Design target value and no measurement was made.
Continued on next page.
No.A0606-2/12
LB11693JH
Continued from preceding page.
Ratings
Parameter
[PWM Oscillator Circuit]
High-level output voltage
Low-level output voltage
Amplitude
External capacitor charge current
Oscillator frequency
[TOC Pin]
Input voltage 1
Input voltage 2
Input voltage 1L
Input voltage 2L
Input voltage 1H
Input voltage 2H
[RD Pin]
Low-level output voltage
Output leakage current
[FG Pin]
Low-level output voltage
Output leakage current
[FGFIL Pin]
Charge current
Discharge current
[FG Amplifier Schmitt Block (IN1)]
Amplifier gain
Hysteresis
[S/S Pin]
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis
High-level input current
Low-level input current
[PWMIN Pin]
Input frequency range
High-level input voltage range
Low-level input voltage range
Input open voltage
Hysteresis
High-level input current
Low-level input current
[F/R Pin]
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis
High-level input current
Low-level input current
VIH(FR)
VIL(FR)
VIO(FR)
VIS(FR)
IIH(FR)
IIL(FR)
VF/R = VREG
VF/R = 0V
2.0
0
VREG-0.5
0.16
-10
-165
0.25
0
-115
VREG
1.0
VREG
0.34
10
V
V
V
V
μA
μA
f(PI)
VIH(PI)
VIL(PI)
VIO(PI)
VIS(PI)
IIH(PI)
IIL(PI)
VPWMIN = VREG
VPWMIN = 0V
-170
2.0
0
2.6
0.16
2.9
0.25
100
-130
50
VREG
1.0
3.2
0.34
130
kHz
V
V
V
V
μA
μA
VIH(SS)
VIL(SS)
VIO(SS)
VIS(SS)
IIH(SS)
IIL(SS)
VS/S = VREG
VS/S = 0V
-170
2.0
0
2.6
0.16
2.9
0.25
100
-130
VREG
1.0
3.2
0.34
130
V
V
V
V
μA
μA
G(FG)
VIS(FG)
Design target value*.
Design target value*. Input equivalent
7
8
Times
mV
IFGFIL1
IFGFIL2
-7
3
-5
5
-3
7
μA
μA
VOL(FG)
IL(FG)
IFG = 5mA
VFG = 28V
0.1
0.3
10
V
μA
VOL(RD)
IL(RD)
IRD = 5mA
VRD = 28V
0.1
0.3
10
V
μA
VTOC1
VTOC2
VTOC1L
VTOC2L
VTOC1H
VTOC2H
Output duty: 100%
Output duty: 0%
Design target value*. 100% when VREG = 4.7V
Design target value*. 0% when VREG = 4.7V
Design target value*. 100% when VREG = 5.3V
Design target value*. 0% when VREG = 5.3V
2.72
1.07
2.72
1.07
3.08
1.21
3.0
1.3
2.80
1.17
3.20
1.33
3.30
1.45
2.90
1.27
3.30
1.45
V
V
V
V
V
V
VOH(PWM)
VOL(PWM)
V(PWM)
ICHG
f(PWM)
VPWM = 2.1V
C = 2200pF
2.75
1.1
1.5
-125
15.5
3.0
1.3
1.7
-90
19.5
3.25
1.4
2.0
-70
27.0
V
V
Vp-p
μA
kHz
Symbol
Conditions
min
typ
max
unit
*: Design target value and no measurement was made.
No.A0606-3/12
LB11693JH
Package Dimensions
unit : mm (typ)
3251
17.8
(6.2)
36
19
2.4
Pd max - Ta
Mounted on a specified board:
114.3mm×76.1mm×1.6mm glass epoxy
Allowable Power Dissipation, Pd max - W
2.1
2.0
(4.9)
7.9
10.5
1.6
1.2
(0.5)
0.8
2.0
0.3
0.25
(2.25)
0.65
1
18
Independent IC
0.9
0.8
1.09
0.4
0.47
2.45max
2.7
0.1
0
-40
-20
0
20
40
60
80
100
Ambient Temperature, Ta -°C
ILB01760
SANYO : HSOP36R(375mil)
Truth Table
Source→Sink
IN1
1
2
3
4
5
6
OUT2→OUT1
OUT3→OUT1
OUT3→OUT2
OUT1→OUT2
OUT1→OUT3
OUT2→OUT3
H
H
H
L
L
L
F/R = ”L”
IN2
L
L
H
H
H
L
IN3
H
L
L
L
H
H
IN1
L
L
L
H
H
H
F/R = “H”
IN2
H
H
L
L
L
H
IN3
L
H
H
H
L
L
Pin Assignment
FRAME
OUT1
GND1
OUT2
PWM
IN3+
IN2+
IN1+
IN3-
IN2-
IN1-
TOC
F/R
NC
S/S
20
17
RD
EI+
NC
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
19
1
NC
2
OUT3
3
NC
4
GND2
5
NC
6
NC
7
VD
8
VCC
9
FRAME
VM
10
VREG
11
LVS
12
FGFIL
13
NC
14
FC
15
CSD
16
FG
18
PWMIN
Top view
No.A0606-4/12
NC
EI-
LB11693JH
Block Diagram
EI-
-
+
FG
TOC
FG
FG
CIRCUIT
CSD
CSD
CIRCUIT
RD
RD FC
LVS
RD
LVSD
VCC
TSD
VD Rd
VM Rf
VCC
CTL
EI+
CTL AMP
PWM
PWM
OSC
COMP
CURR
LIM
PWMIN
PWMIN
CONTROL
CIRCUIT
DRIVER
VREF
FILTER
HALL AMP
& MATRIX
OUT1
GND1
BGP
OUT2
5VREG
S/S
F/R
OUT3
VREG
S/S
F/R
FGFIL
VREG
IN1
IN2
IN3
GND2
Pin Functions
Pin
No.
34
36
2
4
Symbol
OUT1
OUT2
OUT3
GND2
Motor drive output system ground
Motor drive output
Pin Description
Equivalent Circuit
VCC
VD
300Ω
VM
7
9
7
VD
Low side output transistor drive current supply
9
VM
Motor drive output power supply and output current
detection.
Connect a resistor (Rf) between this pin and VCC.
The output current is limited to a value determined
by the equation IOUT = VRF/Rf.
2
34 36
4
8
10
VCC
VREG
Power supply
(Systems other than the motor drive output)
5V regulator output
Connect a capacitor (about 0.1µF) between this pin and
