MachXO2 Product Family Qualification Summary
Lattice Document # 25 – 106923
February 2017
Lattice Semiconductor Corporation Doc. #25-106923
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1
Dear Customer,
Enclosed is Lattice Semiconductor’s MachXO2 Product Family Qualification Report.
This report was created to assist you in the decision making process of selecting and using our products. The
information contained in this report represents the entire qualification effort for this device family.
The information is drawn from an extensive qualification program of the wafer technology and packaging assembly
processes used to manufacture our products. The program adheres to JEDEC and Automotive Industry standards
for qualification of the technology and device packaging. This program ensures you only receive product that
meets the most demanding requirements for Quality and Reliability.
Your feedback is valuable to Lattice. If you have suggestions to improve this report, or the data included, we
encourage you to contact your Lattice representative.
Sincerely,
James M. Orr
Vice President,
Corporate Quality
Lattice Semiconductor Corporation
Lattice Semiconductor Corporation Doc. #25-106923
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TABLE OF CONTENTS
1.0 INTRODUCTION ....................................................................................................................................4
2.0 LATTI CE PRODUCT QUALIFICATION P ROGRAM .................................................................................5
Figure 2.0.1 Lattice Standard Product Qualification Process Flow.................................................................6
Table 2.0.2 Standard Qualification Testing ................................................................................................8
Table 2.0.3 Industry Standard Qualification Testing for WLCSP Packages.....................................................9
3.0 QUALIFICATION DATA MACHXO2 PRODUCT FAMILY ....................................................................... 10
3.1 M
ACH
XO2 P
RODUCT
F
AMILY
L
IFE
(HTOL) D
ATA
........................................................................................ 10
Table 3.1.1 MachXO2 Product Family Life Results using
Pre-Production
Wafer Fab Process Development
Lots ................................................................................................................................................... 11
Table 3.1.2 MachXO2 Product Family Life Results Run on
Production-Process
Wafer Fabrication Lots ........ 12
3.2 M
ACH
XO2 P
RODUCT
F
AMILY
H
IGH
T
EMPERATURE
R
E TENTION
(HTRX) D
ATA
................................................... 13
Table 3.2.1 MachXO2 High Temperature Retention Results ...................................................................... 13
3.3 M
ACH
XO2 P
RODUCT
F
AMILY
F
LASH
E
NDURANCE
C
YCLING
D
ATA
................................................................... 14
Table 3.3.1 MachXO2 Flash Extended Endurance Results ........................................................................ 14
3.4 M
ACH
XO2 P
RODUCT
F
AMILY
– ESD
AND
L
ATCH
UP D
ATA
........................................................................... 15
Table 3.4.1 MachXO2 ESD-HBM Data ................................................................................................... 15
Table 3.4.1 MachXO2 ESD-HBM Data (continued)................................................................................... 16
Table 3.4.2 MachXO2 ESD-CDM Data ................................................................................................... 17
Table 3.4.2 MachXO2 ESD-CDM Data (continued)................................................................................... 18
Table 3.4.3 MachXO2 I/O Latch Up >100mA @ HOT (105°C) Data ............................................................ 19
Table 3.4.4 MachXO2 Vcc Latch Up >1.5X @ HOT (105°C) Data............................................................... 20
4.0 PACKAGE QUALIFI CATI ON DATA FOR MACHX O2 PRODUCT FAMILY.............................................. 21
Table 4.0.1 Product-Package Qualification-By-Similarity Matrix.................................................................. 22
Table 4.02 WLCSP Package Qualification-By-Similarity Matrix................................................................... 23
4.1 M
ACH
XO2 P
RODUCT
F
AMILY
S
URFACE
M
OUNT
P
RECONDITIONING
T
ESTING
...................................................... 24
Table 4.1.1 Surface Mount Precondition Data.......................................................................................... 25
4.2 M
ACH
XO2 P
RODUCT
F
AMILY
T
EMPERATURE
C
YCLING
D
ATA
......................................................................... 27
Table 4.2.1 Temperature Cycling Data.................................................................................................... 27
Table 4.3.1 Unbiased HAST Data .......................................................................................................... 29
Table 4.4.1 Biased HAST Data .............................................................................................................. 31
Table 4.5.1 MachXO2 High Temperature Storage Life Results................................................................... 33
5.0 BOARD LEV EL RELI ABILITY (BLR) STRESS METHODS ..................................................................... 35
Table 5.0.1 Slow-Temp Cycling, IPC-JEDEC9701 & JEDEC JESD22-A104 condition G, soak mode 2............ 36
Table 5.0.2 Bend Testing, IPC-JEDEC9702 & JEDEC JESD22-B113A ....................................................... 36
Table 5.0.3 Drop & Mechanical Shock Testing, IPC-JEDEC9703 & JEDEC JESD22-B111 / JESD-B104C....... 36
6.0 MACHX O2 PROCESS WAFER LEV EL RELIABILITY (WLR) ................................................................. 37
Table 6.0.1 Wafer Level Reliability (WLR) Results .................................................................................... 37
7.0 MACHX O2 SOFT ERROR RATE DATA ................................................................................................ 38
Table 7.0.1 MachXO2 MEASURED FITs / Mb ......................................................................................... 38
8.0 MACHX O2 ADDITIONAL FAMILY DATA .............................................................................................. 39
Table 8.0.1 MachXO2 Package Assembly Data – BGA , QFN & TQFP ...................................................... 39
9.0 REVISION HISTORY ............................................................................................................................ 40
Table 9.0.1 MachXO2 Product Family Qualification Summary revisions ...................................................... 40
Lattice Semiconductor Corporation Doc. #25-106923
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1.0 INTRODUCTION
The MachXO2 family of ultra-low power, instant-on, non-volatile PLDs has six devices with densities ranging from
256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature
Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre -
engineered source synchronous I/O support, advanced configuration support including dual-boot capability and
hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These
features allow these devices to be used in low cost, high volume consumer and system applications.
The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has
several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on -chip
PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting
in low static power for all members of the family.
The MachXO2 devices are available in three options – ultra low power (ZE) and high performance (HC and HE)
devices. The ultra-low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest.
Similarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest.
HC devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3V or 2.5V.
ZE and HE devices only accept 1.2V as the external VCC supply voltage. With the exception of power supply
voltage all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.
The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space
saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same
package.
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2.0 LATTICE PRODUCT QUALIFICATION PROGRAM
Lattice Semiconductor Corp. maintains a comprehensive reliability qualification program to assure that each
product achieves its reliability goals. After initial qualification, the continued high reliability of Lattice products is
assured through ongoing monitor programs as described in Lattice Semiconductor’s Reliability Monitor Program
Procedure (Doc. #70-101667).
All product qualification plans are generated in conformance with Lattice
Semiconductor’s Qualification Procedure (Doc. #70-100164) with failure analysis performed in conformance with
Lattice Semiconductor’s Failure Analysis Procedure (Doc. #70-100166). Both documents are referenced in Lattice
Semiconductor’s Quality Assurance Manual, which can be obtained upon request from a Lattice Semiconductor
sales office. Figure 2.1 shows the Product Qualification Process Flow.
If failures occur during qualification, an 8D process is used to find root cause and eliminate the failure mode from
the design, materials, or process. The effectiveness of any fix or change is validated through additional testing
as required. Final testing results are reported in the qualification reports.
Failure rates in this reliability report are expressed in FITs. Due to the very low failure rate of integrated circuits,
it is convenient to refer to failures in a population during a period of 10
9
device hours; one failure in 10
9
devic e
hours is defined as one FIT.
Product families are qualified based upon the requirements outlined in Table 2.2.
In general, Lattice
Semiconductor follows the current Joint Electron Device Engineering Council (JEDEC) and Military Standard
testing methods.
Lattice automotive products are qualified and characterized to the Automotive Electronics
Council (AEC) testing requirements and methods. Product family qualification will include products with a wide
range of circuit densities, package types, and package lead counts. Major changes to products, pro cesses, or
vendors require additional qualification before implementation.
The MachXO2 family is the third generation FPGA product family and first 65 nm (CS200FL) Flash Technology
based product offering. The Lattice Semiconductor MachXO2 FPGA product family qualification efforts are based
on the first MachXO2 devices in the family per the Lattice Semiconductor Qualification Procedure, doc#70 -
100164.
Lattice Semiconductor maintains a regular reliability monitor program.
Report can be found at
Product Reliability Monitor Report.
The current Lattice Reliability Monitor
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