LD39300
Ultra low drop BICMOS voltage regulator
Datasheet - production data
Applications
Microprocessor power supply
DSPs power supply
Post regulators for switching power supplies
High efficiency linear regulator
Description
Features
3 A guaranteed output current
Ultra low dropout voltage (200 mV typ.
@ 3 A load, 40 mV typ. @ 600 mA load)
Very low quiescent current (1.2 mA typ.
@ 3 A load, 1 µA max @ 25 °C in off mode)
Logic-controlled electronic shutdown
Current and thermal internal limit
± 1.5 % output voltage tolerance @ 25 °C
Fixed and ADJ output voltages: 1.22 V, ADJ
Temperature range: -40 to 125 °C
Fast dynamic response to line and load
changes
Stable with ceramic capacitor
Available in PPAK and DPAK
Part number
Output voltage
DPAK
LD39300DT12-R
LD39300PT-R
PPAK
1.22 V
ADJ from 1.22 to 5.0 V
The LD39300 is a fast ultra low drop linear
regulator which operates from 2.5 V to 6 V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and low quiescent
current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
Table 1: Device summary
March 2017
DocID13160 Rev 3
1/22
www.st.com
This is information on a product in full production.
Contents
LD39300
Contents
1
2
3
4
5
6
7
Diagram ............................................................................................ 3
Pin configuration ............................................................................. 4
Typical application circuits............................................................. 5
Maximum ratings ............................................................................. 7
Electrical characteristics ................................................................ 8
Typical performance characteristics ........................................... 10
Application notes .......................................................................... 13
7.1
7.2
7.3
7.4
7.5
External capacitors.......................................................................... 13
Input capacitor................................................................................. 13
Output capacitor .............................................................................. 13
Thermal note ................................................................................... 13
Inhibit input operation ...................................................................... 13
DPAK package information ............................................................. 14
PPAK package information ............................................................. 17
PPAK and DPAK packing information ............................................. 19
8
Package information ..................................................................... 14
8.1
8.2
8.3
9
Revision history ............................................................................ 21
2/22
DocID13160 Rev 3
LD39300
Diagram
1
Diagram
Figure 1: Block diagram
(*) Not present on ADJ versions.
DocID13160 Rev 3
3/22
Pin
configuration
LD39300
2
Pin configuration
Figure 2: Pin connections (top view for DPAK and PPAK)
Table 2: Pin description
Pin N°
Symbol
PPAK
5
2
4
1
3
TAB
2
1
3
DPAK
V
SENSE
/N.C.
ADJ
V
I
V
O
V
INH
GND
GND
For fixed versions: Not connected on PPAK
For adjustable version: error amplifier Input pin for V
O
from 1.22 to 5.0 V
LDO input voltage; V
I
from 2.5 V to 6 V, C
I
= 1 µF must be located at a distance of
not more than 0.5’’ from input pin.
LDO output voltage pins, with minimum C
O
= 4.7 µF needed for stability (also refer
to C
O
vs ESR stability chart)
Inhibit input voltage: ON MODE when V
INH
≥ 2 V, OFF MODE when V
INH
≤ 0.3 V
(do not leave floating, not internally pulled down/up)
Common ground
Tab is connected to GND
Note
4/22
DocID13160 Rev 3
LD39300
Typical
application circuits
3
Typical application circuits
C
I
and C
O
capacitors must be placed as close as possible to the IC pins.
Figure 3: LD39300 fixed version with inhibit
Inhibit pin is not internally pulled down/up then it must not be left floating. It
disables the device when connected to GND or to a positive voltage less than
0.3 V.
Figure 4: LD39300 adjustable version
Set R2 as close as possible to 4.7 KΩ.
DocID13160 Rev 3
5/22
模拟电子
