The LE28FW4203 (hereinafter referred to as ‘this device’) is a flash memory that consists of 4,194,304bits(262,144Words x 16bits) and
it can erase and program due to a 3V-single supply voltage. This device features erase suspend/resume functions with which the device can
suspend and resume erase.
During erase is suspended, this device can read or program the cells not to be erased.
The erase unit is
basically 32,768 Words/65,536 Bytes, but erase in a smaller unit, which is 2,048 Words/4,096 Bytes (a small sector), is also possible.
Moreover, this device supports the chip batch erase operation that erases a chip entirely and the multiple sector batch erase operation that
selects multiple sectors to erase them at a time.
Features
Power supply voltage:
2.7V ~ 3.6V
Operation Temperature:
-40ºC ~ +85ºC (Read Operation)
0ºC ~ +70ºC (Erase / Program Operation)
Access time:
Random access: 70ns (Max.)
Hardware ID entry
SDP command entry and A9 High voltage entry.
ID read entry by applying high voltage to A9 is possible as well as the same entry by a command input.
Power consumption
Operation mode (readout): 25 mA (Max.)
Standby mode: 10
µA
(Max.)
Detection of program/erase end
Device status can be determined by Hardware Sequence Flag (Toggle bit/ Data polling) and RY/BY#.
Erase unit
Sector: 32K Words/64K Bytes (Sector volume of the boot sector is different.)
Small sector: 2K Words/4K Byte
Chip: all the memory cells
Package
48-pin TSOP (12 mm × 20 mm) Type I Normal bend
48-ball FBGA (6 mm × 8 mm)
Sector protection:
Program/erase can be prohibited in unit of sector in a given range.
Multiple sector batch erase
After specifying multiple sectors to be erased, all the selected sectors can be erased at a time altogether.
Security Sector range
2K Word/4K Byte Security sector range are available in total except for the memory cell range
Reliability:
W/E endurance: over 10K cycles (Typ. 100K cycles), Data retention period: over 10 years
Product Combination
Part Number
LE28FW4203T-70TE
LE28FW4203T-70BE
LE28FW4203F-70TE
LE28FW4203F-70BE
Boot
Top
Bottom
Top
Bottom
Package
TSOP48
TSOP48
FBGA48
FBGA48
*This device incorporate technology licensed from Silicon Storage Technology, Inc. The SuperFlash is registered trademarks of Silicon
Storage Technology, Inc. This preliminary specification is subject to change without notice.
SANYO Electric Co., Ltd. Semiconductor Business Headquarters
1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
Revision 0.10-October 5, 2004-AY/ay-1/36
4M-Bit Flash Memory
Preliminary Specifications
Figure 1: Function diagram
A17 ~ A0
A-1
Address
Buffer
&
Latch
Row decoder
4,194,304 bits
Memory cell array
Column decoder
CE#
OE#
WE#
BYTE#
Control logic
I/O Buffer &
DATA Latch
RESET#
RD/BY#
DQ15 ~ DQ0
Figure 2: Pin Assignment
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
(Top View)
TSOP48
TYPE 1
Normal Bend
(12mm × 20mm)
(Top View)
6
A13
A12
A14
A15
A16
BYTE#
DQ15
/A-1
DQ13
VSS
5
A9
A8
A10
A11
DQ7
DQ14
DQ6
4
WE#
RY
/BY#
A7
RESET#
NC
NC
DQ5
DQ12
VDD
DQ4
3
NC
NC
NC
DQ2
DQ10
DQ11
DQ3
2
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
1
A3
A
A4
B
A2
C
A1
D
A0
E
CE#
F
OE#
G
VSS
H
FBGA48 (6x8)
SANYO Electric Co., Ltd.
2/36
4M-Bit Flash Memory
Preliminary Specifications
Table 1: Pin descriptions
Symbol
A17 ~ A0
A-1
WE#
OE#
I/O
Input
Input
Input
Function
Pins for address input. These address values are latched inside the device during a write cycle.
High voltage (VID) is applied to A9 when “sector protection 1” is carried out.
This pin enables write operation. It’s active, when WE# = Low level.
This pin enables output buffers. It’s active, when OE# = Low level.
High voltage (VID) is applied to this pin when “sector protection 1” is carried out.
This pin enables the device. It’s active, when CE# = Low level.
It’s in a standby mode, when CE# = High level.
This pin resets the device and sets it into a readout mode.
The device is reset, when “RESET# = Low” is input.
This pin switches between Word mode and Byte mode.
Ready/Busy output
Data output and input pins. While the device is in a read operation, these pins function as output
CE#
Input
RESET#
BYTE#
RY/BY#
DQ15/A-1,
DQ14 ~ DQ0
V
DD
V
SS
NC
Input
Input
Output
Input / Output
pins. During a write cycle, these pins function as input pins and are latched inside. When OE or
CE# is set to high, DQ shifts to High impedance.
Power supply
Ground
This pin supplies 3.0 V-power voltage (2.7V ~ 3.6V) .
This pin supplies 0V.
No connection
Table 2: Pin Input / Output for Each Operation Mode
Operation
Manufacturer Code
Device Code
Read
Standby
Output Disable
Write (Erase/Program)
Write Disable
(1)
(1)
CE#
V
IL
V
IL
V
IL
V
IH
X
V
IL
X
X
OE#
V
IL
V
IL
V
IL
X
V
IH
V
IH
V
IL
X
V
ID(4)
WE#
V
IH
V
IH
V
IH
X
V
IH
V
IL
X
V
IH
Low
Pulse
V
IH
X
X
(3)
A0
V
IL
V
IH
A0
X
X
A0
A0
A0
V
IL
A1
V
IL
V
IL
A1
X
X
A1
A1
A1
V
IH
A2
V
IL
V
IL
A2
X
X
A2
A2
A2
X
A3
V
IL
V
IL
A3
X
X
A3
A3
A3
X
A4
V
IL
V
IL
A4
X
X
A4
A4
A4
X
A5
V
IL
V
IL
A5
X
X
A5
A5
A5
X
A6
V
IL
V
IL
A6
X
X
A6
A6
A6
V
IL
A7
V
IL
V
IL
A7
X
X
A7
A7
A7
X
A9
V
ID(4)
V
ID
(4)
DQ15 ~ 0
(0062h)
(000Bh)
(5)
(000Ch)
D
OUT
High-Z
High-Z
D
IN
D
OUT
High-Z / D
OUT
X
(6)
RESET#
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
A9
X
X
A9
A9
A9
V
ID(4)
V
ID(4)
X
X
Sector Protection 1
(1)
Readout of Sector Protection
Information
(1)
(1)
V
IL
V
IL
X
X
V
IL
X
X
V
IH
X
X
V
IH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
IL
X
X
X
X
X
(Table 3)
X
High-Z
V
IH
V
ID(4)
V
IL
Sector protection suspend
Hardware Reset
(1) Reading a device code and a manufacturer code, protecting sectors, reading sector protection information and suspending sector protection can also be
done by command input. Refer to
Table 3 Software Command Sequence
for those operations by command input.
(2) “X” in this table indicates V
IL
or V
IH.
(3) 100
µ
s- low pulses. Refer to
Figure 23
(4) V
ID
indicates High voltage.
(5) Top Boot
(6) Bottom Boot
SANYO Electric Co., Ltd.
3/36
4M-Bit Flash Memory
Preliminary Specifications
Basic
Function Description
Refer to the following descriptions, and timing diagrams or algorithms specified in descriptions of each item.
(1) Read Operation
For data readout, both CE# and OE# should be set to a low level. If CE# is set to a high level, the chip gets deselected. OE#
functions as a gate to determine whether inner output should be sent to outside. If it is set to a high level, it prohibits output and the output
pins turn to a high impedance state. For the details, refer to the
Readout Timing Chart (Figure 3).
This device has a self-power save function, with which the device automatically turns to a standby status if address input doesn’t change
for more than 150ns during normal cell readout. Consequently I
DD
becomes 2µA (typ). Due to this function, the I
DD
value during readout
changes to 1mA / MHz (typ) that corresponds to an operation frequency. Once an address or any input of a control pin has changed, the self-
power save is automatically cleared. This self-power save function doesn’t lead to a longer access time.
(2) ID read operation
ID read operation reads ID code (manufacturer code and device code). With this function, the device can be identified from outside.
This operation is used, for example, to automatically set a program sequence for programming with a PROM writer. Two ways of ID code
readout are available in this device. The contents of the code to be read compile with
ID code table (Table 4).
The readout timing is the
same as that of memory cell readout.
-a Hardware ID Read Operation
The hardware ID read operation reads ID code by applying high voltage to A9. (V
ID
). Typically, this is used when PROM writer
executes ID code readout. From the lower address of 00h and 01h, a manufacturer code and a device code are read respectively. By
canceling the high voltage in A9, the read operation is restored. For the input waveform at the hardware ID readout, refer to the
Hardware
ID read timing chart (Figure 12).
-b Software ID read operation
The software ID read operation reads the device code without applying high voltage to a chip. Since ID code can be read without
applying high voltage to the address bus, this is effective to identify the device incorporated in the set. To execute the software ID read,
command input of 4-bus cycle is required. In the 4th bus cycle, input 00h or 01h to the lower address. From the addresses of 00h and 01h,
the manufacturer code and the device code are read respectively. To clear the Software ID read operation, the reset command must be
input. For the waveform at the software ID read, refer to the
Software ID read timing chart (Figure 13-a).
To clear the software ID
read mode and to read regular cells,
Reset Operation ((5)-a, (5)-b)
must be executed. The software ID read operation can not be executed
when the device is set to the
(3)-b Fast Program Mode
or
(10) Security Sector Mode.
Table 4 :ID code
Type
Manufacturer code
Top Boot
Device Code
Manufacturer code
Bottom Boot
Device Code
BYTE#
H
L
H
L
H
L
H
L
A7 ~ A0
00h
01h
00h
01h
A-1
X
L
X
L
X
L
X
L
Code (HEX)
0062h
62h
000Bh
0Bh
0062h
62h
000Ch
0Ch
-c Common Flash Interface
This device contains the CFI information to describe the characteristics of the device. To execute the CFI Entry, command input of
only 1-bus cycle is required. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in
Table 10-
a to 10-d.
For the waveform at the CFI, refer to the
CFI Mode Entry timing chart (Figure 13-b).
To clear the CFI mode and to read
regular cells,
Reset Operation ((5)-a, (5)-b)
must be executed. The CFI operation cannot be executed when the device is set to the
(3)-b
Fast Program Mode
or
(10) Security Sector Mode.
SANYO Electric Co., Ltd.
4/36
4M-Bit Flash Memory
Preliminary Specifications
Table 3-a: Software Command Sequence (BYTE# = H Word Mode)
Command Sequence
Bus
Write
Cycle
1
st
Bus
address
XXXh
555h
555h
555h
555h
555h
555h
XXXh
XXXh
XXXh
555h
555h
555h
data
F0h
AAh
AAh
AAh
AAh
AAh
AAh
B0h
30h
60h
AAh
AAh
AAh
2
nd
Bus
address
RA
(1)
2AAh
2AAh
2AAh
2AAh
2AAh
2AAh
data
RD
(2)
55h
55h
55h
55h
55h
55h
3
rd
Bus
address
data
4
th
Bus
address
data
5
th
Bus
address
data
6
th
Bus
address
data
Read/Reset A**
Read/Reset B**
ID Read
Program
Chip Erase
Sector Erase
Small Sector Erase
Erase Suspend
Erase Resume
Sector Protection***
Sector Suspend
Reset of Sector Suspend
Read of Sector Protection
Suspended status
Read of Sector
Protection Information
Fast Program Set
Fast Program
Fast Program Reset
Security Sector Entry
Security Sector Program
Security Sector Erase
Security Sector Reset
CFI Entry
1
3
3
4
6
6
6
1
1
3
4
4
3
555h
555h
555h
555h
555h
555h
F0h
90h
A0h
80h
80h
80h
RA
(1)
IA
(3)
PA
(5)
555h
555h
555h
RD
(2)
ID
(4)
PD
(6)
AAh
AAh
AAh
2AAh
2AAh
2AAh
55h
55h
55h
555h
SA
(7)
SA2
(8)
10h
30h
70h
SPA
(9)
2AAh
2AAh
2AAh
60h
55h
55h
55h
SPA
(9)
555h
555h
555h
40h
E0h
E0h
90h
SPA
(9)
XXXh
XXXh
TA
(11)
SPD
(10)
01h
00h
TD
(12)
3
3
2
2
3
4
6
4
1
555h
555h
XXXh
XXXh
555h
555h
555h
555h
555h
AAh
AAh
A0h
90h
AAh
AAh
AAh
AAh
98h
2AAh
2AAh
PA
(5)
XXXh
2AAh
2AAh
2AAh
2AAh
55h
55h
PD
(6)
F0h
00h
55h
55h
55h
55h
555h
555h
90h
20h
SPA
(9)
SPD
(10)
555h
555h
555h
555h
88h
A0h
80h
90h
PA
(5)
555h
XXXh
PD
(6)
AAh
00h
2AAh
55h
SHRA
(
)
30h
note:
* Valid address pins for inputting command codes are A10 ~ A0. The least significant address is A0, and the valid DQs are DQ7 ~ DQ0.
* Addressed and data are shown in hexadecimal.
* XXXh indicates a discretionary address.
** Two kinds of read/reset command function are identical, and the both set the device to the readout mode.
*** To protect a sector by Software Command Sequence, RESET# must be set to V
